Texas Instruments

2 months ago

RTL Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 12 hours agoStatus: Live

Job Summary

Design and implement register-transfer level (RTL) for complex high-performance SoCs within the MCU organization. You’ll write synthesizable, testable SystemVerilog/VHDL, develop RTL simulation/synthesis testbenches, and collaborate with verification teams to support pre-silicon validation. Own timing and constraint work (SDC/STA), apply low-power RTL techniques, and partner with EDA teams to improve synthesis, place-and-route, and static timing flow efficiency.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Seniority: Mid level

Key Responsibilities

•Define and implement RTL architecture for complex SoCs, selecting coding styles, clocking strategies, and low-power techniques.
•Develop and maintain synthesizable SystemVerilog/VHDL code for digital blocks such as core, peripherals, interfaces, and DMA.
•Create and own RTL simulation and synthesis testbenches, running regression to verify functional correctness and timing closure.
•Perform timing analysis with constraint development (SDC) and static timing analysis (STA), iterating on RTL to meet setup/hold and power budgets.
•Lead power-aware design techniques (clock gating, power domains, voltage scaling) and participate in design reviews, documentation, and RTL quality improvements.

Key Requirements

•B.S. (or M.S.) in Electrical/Electronics/Computer Engineering or a related discipline.
•5+ years of hands-on RTL design experience on high-performance SoCs, preferably MCUs or wireless connectivity devices.
•Strong proficiency in SystemVerilog or VHDL with ability to write clean, synthesizable, and testable RTL.
•Deep understanding of digital design fundamentals including pipelining, state-machine design, bus protocols (AHB/APB/AXI), FIFO, arbitration, and clock domain crossing.
•Experience with synthesis tools (DC/Design Compiler/Innovus) and static timing analysis, with ability to meet performance and power targets.

Education:Bachelor's in Electrical/Electronics/Computer Engineering

Skills:CommunicationStakeholder managementMentoringDesign leadershipCollaboration

Languages:English

Tech Stack:RTLSystemVerilogVHDLUVMSimulationCoverageSynthesis toolsDCDesign CompilerInnovusStatic timing analysisSTASDCCI/CDTclPerlPythonBashAHBAPB

Company Brief

Texas Instruments

Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn

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Texas Instruments

2 months ago

RTL Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 12 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Seniority: Mid level

Key Responsibilities

•Define and implement RTL architecture for complex SoCs, selecting coding styles, clocking strategies, and low-power techniques.
•Develop and maintain synthesizable SystemVerilog/VHDL code for digital blocks such as core, peripherals, interfaces, and DMA.
•Create and own RTL simulation and synthesis testbenches, running regression to verify functional correctness and timing closure.
•Perform timing analysis with constraint development (SDC) and static timing analysis (STA), iterating on RTL to meet setup/hold and power budgets.
•Lead power-aware design techniques (clock gating, power domains, voltage scaling) and participate in design reviews, documentation, and RTL quality improvements.

Key Requirements

•B.S. (or M.S.) in Electrical/Electronics/Computer Engineering or a related discipline.
•5+ years of hands-on RTL design experience on high-performance SoCs, preferably MCUs or wireless connectivity devices.
•Strong proficiency in SystemVerilog or VHDL with ability to write clean, synthesizable, and testable RTL.
•Deep understanding of digital design fundamentals including pipelining, state-machine design, bus protocols (AHB/APB/AXI), FIFO, arbitration, and clock domain crossing.
•Experience with synthesis tools (DC/Design Compiler/Innovus) and static timing analysis, with ability to meet performance and power targets.

Education:Bachelor's in Electrical/Electronics/Computer Engineering

Skills:CommunicationStakeholder managementMentoringDesign leadershipCollaboration

Languages:English

Tech Stack:RTLSystemVerilogVHDLUVMSimulationCoverageSynthesis toolsDCDesign CompilerInnovusStatic timing analysisSTASDCCI/CDTclPerlPythonBashAHBAPB

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn