Senior Serdes System Design Engineer/Architect

Broadcom
Austin, San Jose, Irvine
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 10+ yearsEducation: bachelorsSkills: ["Communication","Documentation","Collaboration","Problem-solving"]

Design and verify high-speed Serdes physical-layer algorithms for 100G+ wireline communications. Develop channel models and simulation suites, translate signal-processing requirements into bit-exact MATLAB and C/C++ system models, and perform vector matching verification with RTL. Build, test, and debug firmware for physical-layer functionality and run lab validation, collaborating with analog/digital ASIC designers and DVT/lab teams.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Broadcom
Broadcom
2 days ago

Senior Serdes System Design Engineer/Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live
Reposted: similar role first listed 4 months ago

Job Summary

Design and verify high-speed Serdes physical-layer algorithms for 100G+ wireline communications. Develop channel models and simulation suites, translate signal-processing requirements into bit-exact MATLAB and C/C++ system models, and perform vector matching verification with RTL. Build, test, and debug firmware for physical-layer functionality and run lab validation, collaborating with analog/digital ASIC designers and DVT/lab teams.
Location: Austin, San Jose, Irvine
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop channel models and run simulations to define Serdes architecture.
  • •Define and document signal-processing block requirements, architecture, and lab test plans.
  • •Develop and verify bit-exact MATLAB and C/C++ system models; run system-level simulation suites for architectural tradeoffs.
  • •Work with the design team on vector matching verification with RTL simulations.
  • •Develop, test, and debug physical-layer firmware and perform lab testing/debug; support documentation and customer-facing materials.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Perks:Health InsuranceDentalVision401kEsppAnnual BonusPaid HolidaysPaid Leave

Key Requirements

  • •B.S.E.E. with 12+ years relevant experience OR M.S.E.E. with 10+ years relevant experience.
  • •Expert knowledge of communication theory and digital signal processing algorithms.
  • •Working knowledge of analog circuit behavior and transmission line theory/S-parameters.
  • •Expert in MATLAB and C/C++ programming with strong hands-on lab skills.
  • •Experience with high-speed CDR PLL design and/or equalization for wireline read-channel applications is a plus.
Experience:10+ yearsHigh-speed communicationsWireline communicationsASIC designDigital signal processing
Education:Bachelor's in Electrical Engineering
Skills:CommunicationDocumentationCollaborationProblem-solving
Tech Stack:SerdesMATLABC/C++FirmwareRTLS-parameterPAMFECAdaptive equalizersCancellersCDR PLLIEEE 802.3OIFPCIe Gen6PCIe Gen7

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn