ASIC Engineer

NVIDIA
Bengaluru, Hyderabad
Full timeFunction: Hardware, Embedded & Systems EngineeringExperience: 3+ yearsEducation: bachelorsSkills: ["Root-cause analysis","Collaboration","Automation","Debug efficiency","Training"]

Develop and deploy RTL design-quality methodologies for NVIDIA CPU programs, improving CDC/RDC, lint, structural checks, and sign-off readiness. Analyze flow results to identify root causes across RTL, constraints, and tools, while defining quality requirements and monitoring regressions and violation trends. Partner with RTL build, DFT, verification, physical-design, and CAD teams to integrate new tooling and automate debug, reporting, waiver management, and training.

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FursaFursa
NVIDIA
NVIDIA
3 days ago

ASIC Engineer

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Last checked: 1 hour agoStatus: Live

Job Summary

Develop and deploy RTL design-quality methodologies for NVIDIA CPU programs, improving CDC/RDC, lint, structural checks, and sign-off readiness. Analyze flow results to identify root causes across RTL, constraints, and tools, while defining quality requirements and monitoring regressions and violation trends. Partner with RTL build, DFT, verification, physical-design, and CAD teams to integrate new tooling and automate debug, reporting, waiver management, and training.
Location: Bengaluru, Hyderabad
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop and deploy RTL design-quality methodologies including CDC, RDC, design auditors/netlist checks, power insertion, lint, and structural checks.
  • •Analyze flow results against design intent to identify root causes across RTL, constraints, tools, and methodology.
  • •Define quality requirements and readiness criteria, tracking regressions, violation trends, and sign-off status.
  • •Collaborate across RTL build, DFT, clocks/reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.
  • •Assess new tool releases and integrate methodology capabilities into project environments, improving debug, waiver management, reporting, and training via automation.

Key Requirements

  • •Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
  • •3+ years of experience in ASIC or SoC RTL design or design-methodology work.
  • •Practical experience with Verilog or SystemVerilog for build, analysis, and debugging.
  • •Knowledge of digital design and microarchitecture (pipelines, FSMs, clock/reset architectures, synchronizers, handshakes, async FIFOs, metastability, power-domain crossings).
  • •Experience with methodology areas such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
Experience:3+ years
Education:Bachelor's
Skills:Root-cause analysisCollaborationAutomationDebug efficiencyTraining
Tech Stack:ASICSoCRTLVerilogSystemVerilogCDCRDCNetlistDesign AuditorsPower InsertionLintLow-power verificationUPFSDCStatic timing analysisFormal verificationEquivalence checkingLinuxPythonTcl

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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