Sr. Staff ASIC Design Engineer

AMD
San Jose
Workplace: HybridFull timeUSD 175,000 - 300,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Detail-oriented","Communication","Problem-solving"]

Develop and support next-generation ASIC design for graphics and compute technologies. Work within the front-end design/integration team to implement and verify DFT architecture and features, including scan insertion and ATPG pattern generation. Validate ATPG patterns via gate-level simulation, analyze test coverage and test cost reduction, and provide post-silicon support to improve bring-up, yield learning, and first-pass success.

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FursaFursa
AMD
AMD
2 days ago

Sr. Staff ASIC Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 22 hours agoStatus: Live

Job Summary

Develop and support next-generation ASIC design for graphics and compute technologies. Work within the front-end design/integration team to implement and verify DFT architecture and features, including scan insertion and ATPG pattern generation. Validate ATPG patterns via gate-level simulation, analyze test coverage and test cost reduction, and provide post-silicon support to improve bring-up, yield learning, and first-pass success.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Implement and verify DFT architecture and features.
  • •Perform scan insertion and ATPG pattern generation.
  • •Verify ATPG patterns using gate-level simulation.
  • •Analyze test coverage and test cost reduction.
  • •Provide post-silicon support to ensure successful bring-up and accelerate yield learning.

Pay and Benefits

Salary: USD 175,000 - 300,000 annually

Key Requirements

  • •Hands-on understanding of Design-for-Test (DFT) methodologies and DFT verification experience (e.g., IEEE 1500, JTAG 1149.x, scan, memory BIST).
  • •Experience with Mentor TestKompress and/or Synopsys TetraMAX/DFTMAX for DFT-related flows.
  • •Experience using VCS simulation tools and scripting with Perl and Shell to support verification and testing tasks.
  • •Experience verifying ATPG patterns using gate-level simulation and contributing to test coverage and test cost reduction analysis.
  • •Bachelor’s or master’s degree in computer engineering, electrical engineering, or a related field.
Education:Bachelor's in Computer engineering, Electrical Engineering, or a related field
Skills:Detail-orientedCommunicationProblem-solving
Languages:English
Tech Stack:Design-for-Test (DFT)IEEE 1500JTAG 1149.xScanMemory BISTMentor TestKompressSynopsys TetraMAXDFTMAXVCSPerlShellVerilog RTL

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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