Principal DFT Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: ["Communication","Mentoring","Teamwork","Problem-solving","Collaboration"]

Senior-level DFT design role focusing on driving DFT methodologies and solutions. You’ll mentor junior engineers, collaborate with cross-functional teams across geographies, and apply strong DFT concepts using industry-standard EDA tools (ATPG, RTL lint, scan insertion) to improve test quality and in-system debug capability.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
7 months ago

Principal DFT Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Senior-level DFT design role focusing on driving DFT methodologies and solutions. You’ll mentor junior engineers, collaborate with cross-functional teams across geographies, and apply strong DFT concepts using industry-standard EDA tools (ATPG, RTL lint, scan insertion) to improve test quality and in-system debug capability.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Interact with cross-functional teams across geographies to align on project deliverables.
  • •Mentor junior engineers and drive innovation/automation in DFT workflows.
  • •Contribute to driving new DFT methodologies and solutions to improve quality, reliability, and in-system test and debug capability.
  • •Engage in RTL2GDS flow activities including synthesis and scan insertion, STA and IR drop.
  • •Provide expertise in post-silicon validation and ATE debugging support as needed.

Key Requirements

  • •BE/B.Tech/M.E/M.Tech with 7+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.
  • •Strong hands-on experience using industry standard EDA Tools; experience with logic simulators from one or more EDA vendors; experience with ATPG tools like Cadence Modus; experience with RTL lint tools like Jasper.
  • •Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement.
  • •Programming in Perl/Tcl/Python or other scripting languages is a plus.
  • •Experience in post silicon validation, ATE debug and support is desired.
Experience:7+ yearsSemiconductorsEDASilicon
Education:Bachelor's
Skills:CommunicationMentoringTeamworkProblem-solvingCollaboration
Tech Stack:PerlTclPythonCadence ModusJasperATPGRTLScan insertionSynthesisSTAIR drop

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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