Principal Design Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 136,500 - 253,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5-7 yearsEducation: bachelorsSkills: ["Leadership","Communication","Teamwork","Problem-solving"]

Lead a team to implement high-performance System-On-Chip (SOC) verification flows using Palladium and Protium, oversee RTL synthesis, floor planning, clock tree construction, timing closure, and collaboration across Front End RTL and Back End Verification teams to tape out SOCs.

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Cadence Design Systems
Cadence Design Systems
2 months ago

Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live

Job Summary

Lead a team to implement high-performance System-On-Chip (SOC) verification flows using Palladium and Protium, oversee RTL synthesis, floor planning, clock tree construction, timing closure, and collaboration across Front End RTL and Back End Verification teams to tape out SOCs.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Lead a team to implement SOCs or sub system chips
  • •Work on RTL synthesis and floor planning
  • •Build clock trees and perform optimizations
  • •Close timing, IR drop and physical verification
  • •Review and Document designs for taping out

Pay and Benefits

Salary: USD 136,500 - 253,500 annually
Perks:401kEquityHealth InsuranceDentalVisionPaid LeaveHolidays

Key Requirements

  • •BS in Electrical Engineering with at least 7 years of experience OR MS with at least 5 years OR PhD with at least 1 year of experience
  • •Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
  • •Experience with advanced technologies like 5nm, 3nm and 2nm nodes
  • •Experience using Linux servers, scripting with Shell/Perl/TCL
  • •Detailed knowledge of industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe
Experience:5-7 yearsSemiconductorsHardware designEDASoC
Education:Bachelor's
Skills:LeadershipCommunicationTeamworkProblem-solving
Tech Stack:InnovusTempusQRCVoltusPegasusLinuxShellPerlTCLPCI ExpressDDRLPDDRSRAMUCIe5nm3nm2nm

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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