Senior SRAM Circuit Design Engineer

Design and validate embedded SRAM macros for NVIDIA chips within the Digital IP (DIP) group. You’ll build transistor-level SRAM circuits, supervise layout and verification, and develop SRAM compiler approaches to automate assembly and validation of multiple unique macros. Collaborate with SOC design, silicon test, and productization partners to meet power, performance, and area goals while preparing new silicon for demanding real-world applications.