Layout ASIC Engineer

Cisco
Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 3-6 yearsEducation: bachelorsSkills: ["Analytical","Problem-solving","Communication","Teamwork"]

Own block-level physical layout for analog and mixed-signal ASICs supporting next-gen 100G/200G/400G per-lambda optical interconnects. Drive the full flow from concept through tapeout—floorplanning, placement, routing, integration, and physical verification—while optimizing for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability. Partner with circuit, packaging, CAD, process, and post-silicon teams to close simulation, meet foundry signoff rules, and support debug.

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FursaFursa
Cisco
Cisco
19 minutes ago

Layout ASIC Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 19 minutes agoStatus: Live
Reposted: similar role first listed 2 weeks ago

Job Summary

Own block-level physical layout for analog and mixed-signal ASICs supporting next-gen 100G/200G/400G per-lambda optical interconnects. Drive the full flow from concept through tapeout—floorplanning, placement, routing, integration, and physical verification—while optimizing for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability. Partner with circuit, packaging, CAD, process, and post-silicon teams to close simulation, meet foundry signoff rules, and support debug.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop and implement physical layouts for analog and mixed-signal circuits, high-speed interfaces (SerDes, PAM4), and supporting digital blocks.
  • •Perform block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs.
  • •Translate schematics and performance targets into optimized physical layouts and optimize for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability.
  • •Ensure foundry compliance with design rules (DRC/LVS/ERC, density, EM/IR, reliability) and support simulation closure using post-layout extraction results.
  • •Support integration and tapeout readiness (database checks and signoff) and assist with post-silicon bring-up/debug and failure analysis for layout-related issues.

Key Requirements

  • •Bachelor’s or Master’s in Electrical Engineering (or equivalent).
  • •3+ years of custom IC layout experience for analog, mixed-signal, or high-speed designs, including block-level work through tapeout.
  • •Hands-on experience with physical verification and parasitic-aware implementation for custom layout.
  • •Proficiency with Cadence Virtuoso and Calibre (or equivalent) and understanding of DRC/LVS/ERC and physical signoff flows.
  • •Experience with analog/mixed-signal layout fundamentals (matching, symmetry, shielding, parasitic control, thermal management) and scripting for layout automation (Python, Perl, or TCL) is a plus.
Experience:3-6 yearsASICOptical interconnectsAnalog designMixed-signalHigh-speed
Education:Bachelor's in Electrical Engineering
Skills:AnalyticalProblem-solvingCommunicationTeamwork
Tech Stack:ASICCadence VirtuosoCalibreDRCLVSERCParasitic extractionEM/IR analysisPythonPerlTCLLinuxSerDesPAM4D2D PHYFloorplanningPlacementRoutingTapeout

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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