Principal Analog Circuit Design Engineer - SerDes
Intel
Santa Clara, Phoenix
Workplace: HybridFull timeUSD 220,920 - 311,890 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Cadence Virtuoso","HSPICE","Verilog-A","MATLAB","Python","FinFET CMOS","SerDes","PCIe","Ethernet","CMOS","Noise","Jitter","Matching","Stability","Linearity"]Lead design and validation of cutting-edge analog circuits for high-speed SerDes (112G/224G) in a cross-functional, fast-paced environment. Provide technical direction and mentorship to layout and junior engineers, collaborate with systems, digital design, and test teams, and drive silicon bring-up, post-silicon validation, and robust design in FinFET CMOS processes.
