Lead Application Engineer

Cadence Design Systems
Taiwan
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 5+ yearsEducation: mastersSkills: ["Problem-solving","Communication","Presentation","Customer engagement"]

Engage with customers to understand verification challenges and deliver AI-assisted verification use cases. Build and optimize SystemVerilog/UVM verification environments for IP, subsystem, and SoC designs, including reusable AI-enabled prompts, agents, scripts, and automated workflows. Evaluate solutions through benchmarks, demos, workshops, and training, while troubleshooting UVM, simulation, AI integration, and verification flow issues. Collaborate across R&D, Product Engineering, and support teams to address customer needs and create reference flows and best practices.

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Cadence Design Systems
Cadence Design Systems
6 hours ago

Lead Application Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live
Reposted: similar role first listed 10 months ago

Job Summary

Engage with customers to understand verification challenges and deliver AI-assisted verification use cases. Build and optimize SystemVerilog/UVM verification environments for IP, subsystem, and SoC designs, including reusable AI-enabled prompts, agents, scripts, and automated workflows. Evaluate solutions through benchmarks, demos, workshops, and training, while troubleshooting UVM, simulation, AI integration, and verification flow issues. Collaborate across R&D, Product Engineering, and support teams to address customer needs and create reference flows and best practices.
Location: Taiwan
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Engage with customers to understand verification challenges and identify suitable AI-assisted verification use cases, including UVM testbench and component generation.
  • •Develop and optimize SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC designs.
  • •Develop reusable prompts, skills, agents, scripts, and AI-assisted workflows for customer applications.
  • •Perform technical evaluations, benchmarks, demonstrations, workshops, and customer training.
  • •Troubleshoot UVM, simulation, AI integration, and verification flow issues, and collaborate with R&D, Product Engineering, and support teams to resolve customer requirements.

Key Requirements

  • •MS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • •5+ years of experience in digital design, functional verification, or EDA application engineering.
  • •Strong hands-on SystemVerilog and UVM experience.
  • •Experience developing UVM environments (agents, sequences, scoreboards, reference models, functional coverage, register models).
  • •Strong scripting skills in Python, TCL, shell scripting, or Perl.
Experience:5+ yearsEDADigital designFunctional verification
Education:Master's
Skills:Problem-solvingCommunicationPresentationCustomer engagement
Tech Stack:SystemVerilogUVMPythonTCLShell scriptingPerlXceliumVerisiumVIPAILLM APIsPrompt engineeringRAGVector databasesAgent-based workflowsMCPTool-calling frameworksConstrained-random verificationCoverage-driven verificationUPF

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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