Cadence Design Systems

1 month ago

RTL2 GDS, Sr Principal AE

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Expert Digital Implementation and Signoff Field Applications Engineer guiding customers through Backend Digital Design Implementation, Place & Route, and signoff to achieve design closure and meet project schedules. Collaborates with R&D to influence next-gen Cadence tools, drives evaluations and demonstrations, and enables adoption of Cadence technologies across customer engagements.

Location: United States

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Be part of team of Application Engineers providing technical support to Cadence customers in Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff.
•Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules.
•Collaborate with team to conduct technical presentations and product demonstrations.
•Drive technical evaluations/benchmarks to success.
•Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements.

Pay and Benefits

Salary: USD 126,000 - 234,000 annually

Equity and Bonus:Equity

Perks:401kEquity

Key Requirements

•10+ years of industry Physical Design experience.
•BS degree Computer Science/Engineering, Electrical, Engineering, or related field.
•Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.
•Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure.
•Experience with advanced nodes 10nm and below.

Experience:10+ yearsPhysical DesignIC digital implementationPlace and RouteSignoffTimingPower closure

Education:Bachelor's

Skills:CommunicationProblem-solvingCustomer-facingTeam collaborationLearning agility

Languages:English

Tech Stack:TclPerlPythonPlace and RouteSignoffIR DropDFTLogic Equivalence CheckingGenusInnovusConformal

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

RTL2 GDS, Sr Principal AE

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: United States

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Be part of team of Application Engineers providing technical support to Cadence customers in Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff.
•Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules.
•Collaborate with team to conduct technical presentations and product demonstrations.
•Drive technical evaluations/benchmarks to success.
•Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements.

Pay and Benefits

Salary: USD 126,000 - 234,000 annually

Equity and Bonus:Equity

Perks:401kEquity

Key Requirements

•10+ years of industry Physical Design experience.
•BS degree Computer Science/Engineering, Electrical, Engineering, or related field.
•Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.
•Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure.
•Experience with advanced nodes 10nm and below.

Experience:10+ yearsPhysical DesignIC digital implementationPlace and RouteSignoffTimingPower closure

Education:Bachelor's

Skills:CommunicationProblem-solvingCustomer-facingTeam collaborationLearning agility

Languages:English

Tech Stack:TclPerlPythonPlace and RouteSignoffIR DropDFTLogic Equivalence CheckingGenusInnovusConformal

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor