I/O Design Engineer

Broadcom
United States
Workplace: OnsiteFull timeUSD 109,700 - 175,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: mastersSkills: ["Collaboration","Technical communication","Simulation-driven design","Systems thinking"]

Design and verify CMOS I/O and mixed-signal blocks for leading-edge AI and customer chips. You’ll develop bandgaps, op-amps, comparators, and power-on-reset circuits; run simulations for performance, jitter, and signal integrity; analyze reliability, EMIR, and power. Partner with layout teams to support physical design, build Verilog/Liberty/IBIS models, and contribute to chip integration and silicon bring-up.

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FursaFursa
Broadcom
Broadcom
1 day ago

I/O Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Design and verify CMOS I/O and mixed-signal blocks for leading-edge AI and customer chips. You’ll develop bandgaps, op-amps, comparators, and power-on-reset circuits; run simulations for performance, jitter, and signal integrity; analyze reliability, EMIR, and power. Partner with layout teams to support physical design, build Verilog/Liberty/IBIS models, and contribute to chip integration and silicon bring-up.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design CMOS I/O and mixed-signal circuits including bandgap references, op-amps, comparators, and power-on-reset circuits.
  • •Run AC/DC simulations to validate performance, signal integrity, jitter, and power.
  • •Perform transistor reliability and EMIR analysis.
  • •Create Verilog, Synopsys Liberty, and IBIS models and maintain technical documentation (datasheets, application notes, integration guides).
  • •Support layout, chip integration, and silicon bring-up for test chips and customer products.

Pay and Benefits

Salary: USD 109,700 - 175,500 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEquityEmployee AssistancePaid HolidaysPaid Leave

Key Requirements

  • •MS or PhD in Electrical Engineering.
  • •6+ years of I/O or analog circuit design experience.
  • •Deep proficiency in Cadence Virtuoso schematic/layout and SPICE/Spectre simulation.
  • •Strong knowledge of I/O protocols including GPIO, I2C, I3C, eMMC, RGMII, and SPMI.
  • •Familiarity with ESD, latch-up, EMI, signal integrity, and advanced CMOS FinFET/GAA process nodes.
Experience:6+ yearsAnalog and mixed-signal IC designAI programsAdvanced CMOS process nodes
Education:Master's in Electrical Engineering
Skills:CollaborationTechnical communicationSimulation-driven designSystems thinking
Tech Stack:Cadence VirtuosoSPICESpectreVerilogSynopsys LibertyIBISCMOSFinFETGAAGPIOI2CI3CEMMCRGMIISPMIESDLatch-upEMISignal Integrity

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn