Lead Design Engineer

Cadence Design Systems
Beijing
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Physical design","Floorplanning","Clock tree synthesis","Place-and-route","Timing closure","DRC","LVS","Antenna","EM/IR signoff","DFM","Low power","High speed","PHY IP","Methodology","Flows"]

Lead Design Engineer responsible for end-to-end physical design of semiconductor PHY IP in Beijing. You will perform floor planning, power grid design, place-and-route, clock tree synthesis, timing closure, and signoff for power, signal integrity, DFM, and EM/IR. You’ll contribute to or lead next-generation designs, developing methodologies and flows to optimize low-power, high-speed silicon.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
4 months ago

Lead Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Lead Design Engineer responsible for end-to-end physical design of semiconductor PHY IP in Beijing. You will perform floor planning, power grid design, place-and-route, clock tree synthesis, timing closure, and signoff for power, signal integrity, DFM, and EM/IR. You’ll contribute to or lead next-generation designs, developing methodologies and flows to optimize low-power, high-speed silicon.
Location: Beijing
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Perform physical design implementation tasks including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
  • •Work on varieties of challenging designs, including low power and high speed design, and contribute to next generation PHY IP physical design, methodology and flow development.

Key Requirements

Experience:SemiconductorHardware designIC design
Skills:Physical designFloorplanningClock tree synthesisPlace-and-routeTiming closureDRCLVSAntennaEM/IR signoffDFMLow powerHigh speedPHY IPMethodologyFlows
Tech Stack:Physical designEDADFMTiming closureClock tree synthesisPlace and routeFloorplanningDRCLVSEM/IR signoff

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor