Lead Design Engineer
Cadence Design Systems
Beijing
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Physical design","Floorplanning","Clock tree synthesis","Place-and-route","Timing closure","DRC","LVS","Antenna","EM/IR signoff","DFM","Low power","High speed","PHY IP","Methodology","Flows"]Lead Design Engineer responsible for end-to-end physical design of semiconductor PHY IP in Beijing. You will perform floor planning, power grid design, place-and-route, clock tree synthesis, timing closure, and signoff for power, signal integrity, DFM, and EM/IR. You’ll contribute to or lead next-generation designs, developing methodologies and flows to optimize low-power, high-speed silicon.
