Senior FPGA Engineer, Cyber

Anduril
Washington
Workplace: OnsiteFull timeUSD 166,000 - 220,000 annuallyFunction: CybersecuritySkills: ["Written communication","Verbal communication","Cross-functional collaboration","Technical design-review communication","Hands-on lab debugging"]

Design and implement high-throughput FPGA datapaths and timing-sensitive interfaces for cyber operations at the edge. Own RTL design through simulation, verification, and lab bring-up using VHDL/Verilog/SystemVerilog, and collaborate across DSP, software, hardware, and systems engineering to translate algorithm and interface requirements into robust FPGA implementations. Drive precision timing and throughput closure, document designs for long-term maintainability, and support lab debugging and technical trade studies.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Anduril
Anduril
3 days ago

Senior FPGA Engineer, Cyber

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Design and implement high-throughput FPGA datapaths and timing-sensitive interfaces for cyber operations at the edge. Own RTL design through simulation, verification, and lab bring-up using VHDL/Verilog/SystemVerilog, and collaborate across DSP, software, hardware, and systems engineering to translate algorithm and interface requirements into robust FPGA implementations. Drive precision timing and throughput closure, document designs for long-term maintainability, and support lab debugging and technical trade studies.
Location: Washington
Workplace: Onsite
Employment Type: Full time
Job Function: Cybersecurity
Seniority: Mid level

Key Responsibilities

  • •Design and implement high-throughput FPGA datapaths, packetization pipelines, timing-sensitive interfaces, and hardware-near acceleration blocks.
  • •Own RTL design, simulation, verification, and lab bring-up across VHDL/Verilog/SystemVerilog workflows.
  • •Collaborate with DSP, software, hardware, and systems engineers to turn algorithm and interface requirements into robust FPGA implementations.
  • •Drive precision timing, synchronization, and throughput closure for the selected FPGA/SoC platform and adjacent high-speed digital interfaces.
  • •Document architectures, interfaces, and verification approaches and support design reviews, technical trade studies, and lab debugging.

Pay and Benefits

Salary: USD 166,000 - 220,000 annually
Equity and Bonus:Equity

Key Requirements

  • •Deep experience with FPGA development on Xilinx or comparable platforms, including SoC/MPSoC-based or other high-performance digital devices for SDR systems.
  • •Proficiency in VHDL, Verilog, or SystemVerilog, including simulation, timing closure, and resource/performance tradeoffs.
  • •Experience building high-speed digital interfaces and datapaths such as Ethernet-based packet movement, DMA-adjacent flows, or streaming signal pipelines.
  • •Hands-on familiarity with precision timing, synchronization, sysref/clocking concepts, and deterministic interface behavior.
  • •Ability to collaborate with software and DSP engineers on register interfaces and integration boundaries, including debugging in the lab with instrumentation (oscilloscopes, logic analyzers, spectrum analyzers).
Skills:Written communicationVerbal communicationCross-functional collaborationTechnical design-review communicationHands-on lab debugging
Tech Stack:FPGAXilinxSoCMPSoCVHDLVerilogSystemVerilogRTLSimulationTiming closureEthernetDMAStreaming signal pipelinesSysrefClockingCocotbGitLab CI/CDFFTChannelizationPSD generation

Company Brief

Anduril
Designs and builds advanced defense systems combining autonomous aircraft, sensors, and AI-driven software for military and national security applications, focused on modernizing battlefield capabilities and distributed sensing.
Industry: Defense Technology
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series E+
Headquarters: Costa Mesa, United States
Founded: 2017
WebsiteLinkedIn