Senior ASIC Verification Engineer
Austin
Full timeUSD 136,000 - 264,500 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 3+ yearsSkills: ["SystemVerilog","UVM","Python","Verilog","VCS","Verdi","OOPS"]Experienced ASIC verification engineer focusing on system-level IP verification for RTL designs, developing robust verification environments, UVM-based testbenches, and automated regression to meet DV milestones across unit, sub-system, and SOC levels.
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