Cadence Design Systems

3 weeks ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Lead DV verification for ASIC/SoC projects, designing scalable, reusable testbenches and driving verification strategy across teams. You’ll guide feature extraction from architectural specs, lead complex debug efforts, and ensure high functional coverage using SystemVerilog/UVM, with familiarity in bus protocols and formal verification to deliver robust silicon solutions.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Strategy and Architecture: Define the overall verification strategy (typically UVM/SystemVerilog), tools, and infrastructure; design scalable verification environments with BFMs, monitors, scoreboards, and checkers; extract critical features from architectural specs for robust testing.
•Execution and Technical Leadership: Technically lead DV execution of small to mid-sized customer ASIC projects; convert high-level requirements into DV execution plan; write complex test cases and sequences to achieve high functional coverage; lead root-cause analysis and implement fixes; implement constrained-random stimulus generation; apply formal verification to prove properties.
•Metric Management: Monitor and analyze functional and code coverage metrics; oversee gate-level simulations to verify timing and resets; define the definition of done and provide final technical sign-off for the verification phase.
•Soft Skills and Leadership: Mentor junior engineers on coding standards and debugging techniques; act as the primary technical contact between design, architecture, and emulation teams; collaborate cross-functionally and manage project timelines and risks.
•Project Management: Manage timelines, identify risks in the verification schedule, and prioritize tasks to meet project deadlines.

Key Requirements

•BE/B.Tech or M.Tech/MS in Electronics, VLSI, or related field
•7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies
•Deep expertise in SystemVerilog and UVM (Universal Verification Methodology)
•Strong understanding of digital design fundamentals — RTL, timing, clocking, resets
•Experience with industry-standard simulators: Xcelium, VCS, Questa

Experience:7-10 yearsSemiconductorASICSoCVerification

Education:Bachelor's in Electronics, VLSI

Skills:SystemVerilogUVMTestbenchVerificationDebuggingWaveform analysisGLSUPF/CPFFormal verificationAXIAHBAPBPCIeDDR

Tech Stack:SystemVerilogUVMXceliumVCSQuestaAXIAHBAPBPCIeDDRVerisiumSimVisionUPFCPF

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

Cadence Design Systems

3 weeks ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Strategy and Architecture: Define the overall verification strategy (typically UVM/SystemVerilog), tools, and infrastructure; design scalable verification environments with BFMs, monitors, scoreboards, and checkers; extract critical features from architectural specs for robust testing.
•Execution and Technical Leadership: Technically lead DV execution of small to mid-sized customer ASIC projects; convert high-level requirements into DV execution plan; write complex test cases and sequences to achieve high functional coverage; lead root-cause analysis and implement fixes; implement constrained-random stimulus generation; apply formal verification to prove properties.
•Metric Management: Monitor and analyze functional and code coverage metrics; oversee gate-level simulations to verify timing and resets; define the definition of done and provide final technical sign-off for the verification phase.
•Soft Skills and Leadership: Mentor junior engineers on coding standards and debugging techniques; act as the primary technical contact between design, architecture, and emulation teams; collaborate cross-functionally and manage project timelines and risks.
•Project Management: Manage timelines, identify risks in the verification schedule, and prioritize tasks to meet project deadlines.

Key Requirements

•BE/B.Tech or M.Tech/MS in Electronics, VLSI, or related field
•7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies
•Deep expertise in SystemVerilog and UVM (Universal Verification Methodology)
•Strong understanding of digital design fundamentals — RTL, timing, clocking, resets
•Experience with industry-standard simulators: Xcelium, VCS, Questa

Experience:7-10 yearsSemiconductorASICSoCVerification

Education:Bachelor's in Electronics, VLSI

Skills:SystemVerilogUVMTestbenchVerificationDebuggingWaveform analysisGLSUPF/CPFFormal verificationAXIAHBAPBPCIeDDR

Tech Stack:SystemVerilogUVMXceliumVCSQuestaAXIAHBAPBPCIeDDRVerisiumSimVisionUPFCPF

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor