Senior Staff Front End Automation Engineer

AMD
Penang
Workplace: HybridFull timeMYR 185,500 - 265,000 annuallyFunction: QA, Test & Release EngineeringExperience: 12+ yearsSkills: ["Technical leadership","Mentorship","Cross-functional collaboration","Communication","Technical enablement"]

Lead the roadmap for front-end EDA verification and signoff flows, including RTL lint/design-quality, static timing analysis (STA) with constraints, and CDC/RDC signoff. Drive AI-based modernization by applying ML and agentic automation to triage, timing/constraint debugging, and regression analysis. Act as a technical resource and mentor for FE flow methodology, enable users with UPF and timing-flow guidance, and partner across design, CAD, IP, and library teams to maintain regression/CI quality.

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FursaFursa
AMD
AMD
2 days ago

Senior Staff Front End Automation Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Lead the roadmap for front-end EDA verification and signoff flows, including RTL lint/design-quality, static timing analysis (STA) with constraints, and CDC/RDC signoff. Drive AI-based modernization by applying ML and agentic automation to triage, timing/constraint debugging, and regression analysis. Act as a technical resource and mentor for FE flow methodology, enable users with UPF and timing-flow guidance, and partner across design, CAD, IP, and library teams to maintain regression/CI quality.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Shape the technical direction and roadmap for front-end flows covering lint/design-quality, STA/constraints, and RTL quality signoff (architecture, enablement, and release strategy).
  • •Drive AI-based modernization by applying ML and agentic automation to lint triage, timing/constraint debug, and regression analysis.
  • •Serve as a technical resource and mentor for FE flow issues, ruleset decisions, and methodology questions from design teams.
  • •Drive user enablement and adoption for UPF and timing-flow enablement, including best-practice guidance and documentation.
  • •Partner with design, CAD, IP, and library teams and maintain regression/CI (e.g., nightly pipelines) for flow quality.

Pay and Benefits

Salary: MYR 185,500 - 265,000 annually

Key Requirements

  • •12+ years in silicon design automation/front-end methodology/RTL flow development with a track record of driving technical initiatives.
  • •Deep expertise in RTL lint/design-quality, static timing analysis and constraint (SDC) development, and RTL quality signoff including CDC.
  • •Strong understanding of the RTL-to-signoff flow and how front-end deliverables feed physical implementation.
  • •Proficient scripting with Tcl, Python, and Perl, and comfort with flow infrastructure and regression/CI (e.g., Jenkins).
  • •Hands-on with industry front-end EDA tools (Synopsys/Cadence) for STA, lint, and CDC, plus experience applying AI/ML/LLM-based agents to EDA flows or automation.
Experience:12+ yearsSilicon design automationFront-end methodologyRTL flow developmentEDAASICSoCAI/ML for automation
Skills:Technical leadershipMentorshipCross-functional collaborationCommunicationTechnical enablement
Languages:English
Tech Stack:TclPythonPerlJenkinsSynopsysCadenceSDCSTARTL lintCDCRDCUPFRTL quality signoffMachine learningLLMAgentic automationPerforceICManage

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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