ASIC DFT Engineer

Cisco
Bengaluru, Chennai, Hyderabad
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 4-8 yearsEducation: bachelorsSkills: ["Debugging","Problem-solving","Verbal communication","Collaboration"]

Implement Hardware Design-for-Test (DFT) features that enable ATE, in-system test, debug, and diagnostics for Cisco silicon designs. Develop innovative DFT IP and collaborate with design, verification, and PD teams to integrate and validate test logic across implementation phases and post-silicon validation. Work with hardware DFT and physical design efforts for new silicon device models while creating reusable test and debug strategies, with strong independent problem-solving.

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FursaFursa
Cisco
Cisco
3 days ago

ASIC DFT Engineer

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Last checked: 12 hours agoStatus: Live

Job Summary

Implement Hardware Design-for-Test (DFT) features that enable ATE, in-system test, debug, and diagnostics for Cisco silicon designs. Develop innovative DFT IP and collaborate with design, verification, and PD teams to integrate and validate test logic across implementation phases and post-silicon validation. Work with hardware DFT and physical design efforts for new silicon device models while creating reusable test and debug strategies, with strong independent problem-solving.
Location: Bengaluru, Chennai, Hyderabad
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Implement Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics needs.
  • •Develop DFT IP in collaboration with cross-functional teams and support full chip design integration with testability coordinated in RTL.
  • •Partner with design, design-verification, and PD teams to integrate and validate test logic across implementation phases and post-silicon validation flows.
  • •Contribute to creation of innovative hardware DFT and physical design aspects for new silicon device models and reusable test and debug strategies.
  • •Craft solutions and debug with minimal mentorship.

Key Requirements

  • •Bachelor's or Master's degree in Electrical or Computer Engineering with 4-8 years of experience.
  • •Knowledge of innovative trends in DFT, test, and silicon engineering.
  • •Experience with JTAG protocols and Scan/BIST architectures, including memory BIST and boundary scan.
  • •Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime.
  • •Verification skills including SystemVerilog logic equivalence checking and validating test timing; experience with gate-level simulation and debugging with VCS.
Experience:4-8 years
Education:Bachelor's in Electrical or Computer Engineering
Skills:DebuggingProblem-solvingVerbal communicationCollaboration
Tech Stack:DFTATEJTAGScanBISTMemory BISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeSystemVerilogLogic equivalency checkingVCSGate-level simulationTclPythonPerlP1687

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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