Design Engineer II

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 2-10 yearsEducation: bachelorsSkills: ["Leadership","Multi-priority management","Clear communication","Collaboration","Debugging"]

Own key activities for characterizing and validating analog and digital IP-based silicon solutions, leading lab tests and silicon characterization with a small engineering team. Build and execute post-silicon PHY, systems interop, and compliance test suites for high-speed SERDES standards such as Ethernet/PCIe/UCIe, using lab equipment to debug, root cause, and analyze failures. Collaborate with R&D and Marketing to define scope and deliver results on time, including reliability qualification testing and Verilog RTL development.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
4 days ago

Design Engineer II

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Own key activities for characterizing and validating analog and digital IP-based silicon solutions, leading lab tests and silicon characterization with a small engineering team. Build and execute post-silicon PHY, systems interop, and compliance test suites for high-speed SERDES standards such as Ethernet/PCIe/UCIe, using lab equipment to debug, root cause, and analyze failures. Collaborate with R&D and Marketing to define scope and deliver results on time, including reliability qualification testing and Verilog RTL development.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead daily lab tests and silicon characterization activities for analog and digital IP-based silicon solutions.
  • •Develop and interpret standard specifications to build electrical, protocol, interoperability, and compliance test suites.
  • •Isolate PHY and controller (MAC/PCS) features to test and develop calibration/compliance lab suites for characterization.
  • •Debug and root-cause silicon failures using lab equipment and lab automation scripts, including test result analysis.
  • •Coordinate with R&D and Marketing to define test scope and deliver results on time, including reliability qualification tests (ESD/Latchup/HTOL).

Key Requirements

  • •2–10 years of experience with BTech or 10 years with MTech in post-silicon PHY, systems interop, and compliance testing.
  • •5–7 years of management experience leading and mentoring a small team of engineers.
  • •Physical layer and protocol layer experience with at least one high-speed SERDES on Ethernet, PCIe, CXL, or UCIe.
  • •Hands-on debug experience using lab equipment such as oscilloscopes, bit error rate testers, protocol exercisers, and analyzers.
  • •Expert knowledge of Verilog RTL coding for FPGA, plus Python and C/C++ for test and analysis.
Experience:2-10 yearsPost-siliconSilicon characterizationPHYSERDESProtocol testingInteroperability testing
Education:Bachelor's
Skills:LeadershipMulti-priority managementClear communicationCollaborationDebugging
Tech Stack:Post-Silicon PHYSystems InteropCompliance testingHigh speed SERDESEthernetPCIeCXLUCIeUCIe LTSSM statesLTSSMUCIe InterfacesVerilogRTLFPGAOscilloscopesBit Error Rate TestersProtocol ExercisersAnalyzersProtocol ExerciserPrinted circuit boards

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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