Staff Silicon Design Engineer

AMD
Belgrade
Workplace: OnsiteFull timeRSD 5,002,550 - 7,146,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Communication","Analytical thinking","Problem-solving","Team collaboration","Self-starter","Continuous improvement"]

Lead performance verification for a next-generation multi-subsystem NBIO IP across client, server, embedded, graphics, and semi-custom chips. Collaborate with performance architects and RTL/SoC/IP teams to define what to verify, build and enhance UVM/SV testbenches, and create test plans. Drive regression triage and scrum execution, debug root causes in functional/performance failures, and publish performance case-study results for management readouts.

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FursaFursa
AMD
AMD
1 day ago

Staff Silicon Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Lead performance verification for a next-generation multi-subsystem NBIO IP across client, server, embedded, graphics, and semi-custom chips. Collaborate with performance architects and RTL/SoC/IP teams to define what to verify, build and enhance UVM/SV testbenches, and create test plans. Drive regression triage and scrum execution, debug root causes in functional/performance failures, and publish performance case-study results for management readouts.
Location: Belgrade
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Technically lead a small team of engineers responsible for NBIO performance verification across multiple projects.
  • •Collaborate with performance architects and design/verification engineers to understand new performance features to be verified.
  • •Create test plan documentation from hardware use cases and coordinate technical reviews within the team.
  • •Drive regression triage and daily scrum execution, including backlog management and planning.
  • •Debug functional and performance test failures to determine root causes and work with RTL designers and SoC/IP architects to resolve performance issues.

Pay and Benefits

Salary: RSD 5,002,550 - 7,146,500 annually

Key Requirements

  • •5+ years of ASIC design verification experience with strong knowledge of RTL design, verification, and architecture.
  • •Hands-on experience developing or enhancing UVM testbenches and proficiency with UVM and SystemVerilog concepts.
  • •Solid understanding of IP-level ASIC design/verification flow from planning through tape-out.
  • •Strong debugging experience for functional or performance issues in designs.
  • •Proficiency with C/C++ and scripting (Perl, Python, TCL).
Experience:5+ yearsASIC design verificationProcessor architectureUVMRTL verificationSoC/IP
Education:Bachelor's in Computer Science/Computer engineering/Electrical Engineering
Skills:CommunicationAnalytical thinkingProblem-solvingTeam collaborationSelf-starterContinuous improvement
Tech Stack:UVMSystemVerilogSVRTLASICSoCNBIOPCIeCXLI/O VirtualizationsMemory managementX86ARMCC++PerlPythonTCLScrumSystemVerilog concepts

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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