Test Development Engineer

Broadcom
United States
Workplace: OnsiteFull timeUSD 108,000 - 172,800 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","OVM","SVA","Verilog","Python","Shell scripting","Tcl","Automation"]

Senior DMS Verification Engineer to lead testbench architecture and verification methodologies for mixed-signal ASICs/SoCs, drive AI-assisted automation, and coordinate global teams across US and Asia to ensure tape-out readiness and high coverage.

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FursaFursa
Broadcom
Broadcom
3 months ago

Test Development Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 23 hours agoStatus: Live

Job Summary

Senior DMS Verification Engineer to lead testbench architecture and verification methodologies for mixed-signal ASICs/SoCs, drive AI-assisted automation, and coordinate global teams across US and Asia to ensure tape-out readiness and high coverage.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

  • •Architect, develop, and maintain advanced UVM-based testbenches for the functional verification of complex mixed-signal ASIC products.
  • •Champion verification quality by integrating new methodologies, such as SystemVerilog Assertions (SVA) and UVM/OVM, to reduce mixed-signal validation bottlenecks.
  • •Act as the primary liaison between our local US digital design teams and our worldwide verification teams, translating complex specifications into seamless execution.
  • •Lead initiatives to explore and integrate modern automation and AI-assisted verification workflows to accelerate testbench generation and debug efficiency.
  • •Own verification efforts at both the block and system levels for major tape-out projects, driving functional and code coverage to closure.

Pay and Benefits

Salary: USD 108,000 - 172,800 annually
Equity and Bonus:Equity
Perks:MedicalDentalVision401kEsppEapPaid Leave

Key Requirements

  • •5+ years of hands-on experience in digital verification of mixed-signal ASICs or SoCs.
  • •Deep expertise in coverage-driven verification processes and frameworks (UVM/OVM).
  • •Strong understanding of event-driven simulator-based modeling techniques and how digital logic interacts with analog boundaries.
  • •Proven ability to coordinate technical problem-solving across cross-site and global teams; strong English communication skills.
  • •Bachelor's in Electrical Engineering, Computer Engineering, or Computer Science and 8+ years of related experience or Masters degree in Engineering and 6+ years of related experience.
Experience:5+ yearsSemiconductorASICSoCDigital verificationMixed-signal
Education:Bachelor's
Skills:SystemVerilogUVMOVMSVAVerilogPythonShell scriptingTclAutomation
Languages:English
Tech Stack:SystemVerilogUVMOVMSVAPythonVerilogTclShell scripting

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn