IC Design Engineer

Lead Broadcom’s physical design activities to deliver right-first-time silicon, using top-down/bottom-up SoC integration for 5nm and below. Own key P&R flow stages including floorplanning, partitioning, placement, CTS, routing, physical verification, and support STA closure. Implement timing and functional ECO, enhance or adapt automation flows for reuse, and drive improvements in TAT while maintaining quality. Proficiency with Cadence, Synopsys, or Mentor EDA tools and scripting is required.