Senior SOC Physical Design Engineer, HBM

Micron Technology
United States
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3-5 yearsEducation: bachelorsSkills: ["Cross-functional collaboration","Hands-on problem solving","Collaboration"]

Own physical implementation of advanced HBM SoC logic and base die designs, from floorplanning through tapeout, using EDA and signoff workflows. Collaborate across RTL, verification, DFT, packaging, and manufacturing to deliver robust performance, power, and area (PPA) results. Execute timing closure, integrate complex IP blocks, run DRC/LVS/timing signoff, and support post-silicon debug by correlating silicon behavior with physical design data.

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FursaFursa
Micron Technology
Micron Technology
2 months ago

Senior SOC Physical Design Engineer, HBM

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Last checked: 18 hours agoStatus: Live

Job Summary

Own physical implementation of advanced HBM SoC logic and base die designs, from floorplanning through tapeout, using EDA and signoff workflows. Collaborate across RTL, verification, DFT, packaging, and manufacturing to deliver robust performance, power, and area (PPA) results. Execute timing closure, integrate complex IP blocks, run DRC/LVS/timing signoff, and support post-silicon debug by correlating silicon behavior with physical design data.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Support physical implementation of SoC blocks from floorplanning through placement, clock tree synthesis (CTS), routing, and optimization to meet PPA targets.
  • •Assist with setup/hold timing closure across multi-mode, multi-corner (MMMC) scenarios using PrimeTime or Tempus under senior guidance.
  • •Collaborate with RTL and integration teams to ensure correct clocking, reset strategies, and power intent implementation.
  • •Integrate and implement complex IP blocks (controllers, interfaces, MBIST, DFT logic, buffers, PHY-adjacent logic) with focus on timing and physical correctness.
  • •Run and debug physical signoff checks (DRC, LVS, timing signoff), support tapeout readiness (ECO flows and design reviews), and participate in post-silicon debug.

Pay and Benefits

Perks:Health InsuranceDentalVisionPaid LeavePaid Time-off

Key Requirements

  • •Hands-on experience with physical design and signoff EDA tools such as Innovus, Fusion Compiler, IC Validator (ICV), or Calibre.
  • •Strong understanding of static timing analysis fundamentals, clocking concepts, and Synopsys Design Constraints (SDC).
  • •Working knowledge of power intent methods including UPF or CPF, plus power grid planning and basic power integrity considerations.
  • •Familiarity with physical verification/signoff flows such as DRC, LVS, and parasitic awareness.
  • •Minimum three to five years of experience in related physical design or SoC implementation roles.
Experience:3-5 years
Education:Bachelor's in Electrical Engineering, Computer Engineering
Skills:Cross-functional collaborationHands-on problem solvingCollaboration
Tech Stack:InnovusFusion CompilerIC Validator (ICV)CalibrePrimeTimeTempusSynopsys Design Constraints (SDC)UPFCPFDRCLVSTclPythonAnsysGDSII

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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