Senior RTL Design Engineer

Intel
India
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: ["Collaboration","Debugging","Optimization"]

Drive RTL logic design and integration for next-generation high-speed mixed-signal IP, bridging digital architecture with analog/mixed-signal (AMS) circuits. Own critical PHY digital blocks including PCS, calibration engines, power management states, and clock/reset distribution. Define and verify digital-analog interfaces, ensure Data Link compliance (PIPE 5.x/6.x), lead front-end closure (Lint/CDC/LEC/STA), collaborate across DV/AMS simulation teams, and support post-silicon validation and bring-up.

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FursaFursa
Intel
Intel
2 months ago

Senior RTL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Drive RTL logic design and integration for next-generation high-speed mixed-signal IP, bridging digital architecture with analog/mixed-signal (AMS) circuits. Own critical PHY digital blocks including PCS, calibration engines, power management states, and clock/reset distribution. Define and verify digital-analog interfaces, ensure Data Link compliance (PIPE 5.x/6.x), lead front-end closure (Lint/CDC/LEC/STA), collaborate across DV/AMS simulation teams, and support post-silicon validation and bring-up.
Location: India
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own micro-architecture and RTL design for digital control blocks within the PHY, including PCS, calibration engines, power management states (L0s/L1/L2), and clock/reset distribution.
  • •Define, design, and verify digital-analog interface boundaries and implement calibration algorithms for analog components (e.g., RX equalization, TX driver impedance, PLL/DLL tracking loops).
  • •Ensure digital logic integrates with the Data Link layer via standard interfaces (PIPE 5.x/6.x) and adheres to protocol constraints.
  • •Drive front-end implementation activities including linting, CDC analysis, formal verification (LEC), and STA constraints generation.
  • •Support post-silicon validation, bring-up, and debug to root-cause silicon misbehavior and optimize firmware/hardware calibration parameters.

Key Requirements

  • •7+ years of dedicated experience in ASIC/IP RTL design.
  • •Strong knowledge of high-speed SerDes architectures and deep understanding of the PIPE interface standard.
  • •Experience working across digital/analog boundaries, including asynchronous signals, handshaking protocols, and separate analog/digital power domains.
  • •Proficiency with front-end design tools such as Synopsys SpyGlass (Lint/CDC) and Cadence JasperGold (formal verification).
  • •Bachelor's or Master's degree in Electrical Engineering, Electronics and Communication, or related discipline.
Experience:7+ yearsASICRTL designSerDesMixed-signalIP development
Education:Bachelor's in Electrical Engineering, Electronics and Communication, or related discipline
Skills:CollaborationDebuggingOptimization
Tech Stack:System VerilogVerilogPIPE 5.xPIPE 6.xSynopsys SpyGlassCadence JasperGoldUPFClock gatingSTACDC analysisLECASIC/IP RTL design

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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