Principal Product Engineer - Memory IP

Cadence Design Systems
Nanjing, Shanghai
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 7+ yearsEducation: bachelorsSkills: ["Problem-solving","Customer guidance","Technical communication","Analytics","Decision support"]

Support pre-silicon integration, usage, and implementation of memory subsystem products, including internal QA testing for controller + PHY. Troubleshoot and resolve complex application/implementation issues and guide customers. Help with memory PHY and controller SOC integration reviews, RTL and gate-level simulations, timing closure, and physical integration. Contribute to product documentation and checklists, and assist with post-silicon bringup and production test activities as needed.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Principal Product Engineer - Memory IP

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Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Support pre-silicon integration, usage, and implementation of memory subsystem products, including internal QA testing for controller + PHY. Troubleshoot and resolve complex application/implementation issues and guide customers. Help with memory PHY and controller SOC integration reviews, RTL and gate-level simulations, timing closure, and physical integration. Contribute to product documentation and checklists, and assist with post-silicon bringup and production test activities as needed.
Location: Nanjing, Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Support pre-silicon integration, usage, and implementation of memory subsystem products.
  • •Perform internal system integration and QA testing of memory subsystem products (Controller + PHY).
  • •Analyze and resolve complex subsystem application/implementation issues and provide guidance to customers.
  • •Assist with RTL and gate-level simulations, including verification of functionality and support for timing closure and physical integration.
  • •Support product documentation/checklists and, as needed, post-silicon bringup and production test activities for customers.

Key Requirements

  • •B.S. Electrical/Computer Engineering (or similar) with 7+ years experience OR M.S. with 5+ years overall experience.
  • •Experience with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 (or similar) IPs.
  • •Verilog RTL design and gate-level verification experience.
  • •Synthesis and static timing analysis experience, with physical implementation/verification experience a plus.
  • •Familiarity with industry-standard DFT flows and test methodologies; ability to read schematics and participate in SI/PI reviews for customer board/package implementation.
Experience:7+ yearsIP developmentSemiconductorsMemory subsystem
Education:Bachelor's in Electrical/Computer Engineering (or similar)
Skills:Problem-solvingCustomer guidanceTechnical communicationAnalyticsDecision support
Tech Stack:VerilogRTLGate-level simulationDDR5DDR4DDR3LPDDR5LPDDR4LPDDR3HBM3GDDR6SynthesisStatic timing analysisDFTTest methodologiesAI-powered toolsAI-powered analytics

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
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