Sr Principal Design Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 11+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","UVM","AXI","CHI","DDR","PCIe","UCIe","USB"]

Lead memory controller DV group with MDV verification, Constrained Random and Formal Property Verification, and mentor junior engineers. Manage verification environment enhancements, support multi-config regressions, and engage in pre/post‑sales interactions and customer support to ensure design quality and DV methodologies are aligned with customer needs.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
7 months ago

Sr Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Lead memory controller DV group with MDV verification, Constrained Random and Formal Property Verification, and mentor junior engineers. Manage verification environment enhancements, support multi-config regressions, and engage in pre/post‑sales interactions and customer support to ensure design quality and DV methodologies are aligned with customer needs.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Ensure the design aligns with technical and quality requirements and metrics for the team
  • •Participate in technical alignment with verification experts to define verification strategy and architect verification environment
  • •Represent DV and lead team interactions with RTL, Subsystem and Performance for design verification tasks
  • •Contribute to defining, developing, and deploying new functional verification methodologies
  • •Review project signoff and quality of DDR controller feature verification

Key Requirements

  • •11+ years of relevant experience including design verification experience
  • •Strong background in functional verification fundamentals, environment planning, test plan generation, environment development
  • •Strong expertise in Verilog, SystemVerilog (SV) with UVM methodology
  • •AXI and/or CHI experience is highly desirable
  • •BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent
Experience:11+ yearsSemiconductorsHardware designElectronic design
Education:Bachelor's in Electrical/Electronics
Skills:VerilogSystemVerilogUVMAXICHIDDRPCIeUCIeUSB
Tech Stack:VerilogSystemVerilogUVMAXICHIDDRPCIeUCIeUSB

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor