Lead Product Validation Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 3-6 yearsEducation: bachelorsSkills: ["Communication","Presentation","Problem-solving"]

Lead product verification engineer responsible for digital verification of SoC designs, requiring strong HDL knowledge (Verilog/VHDL), SystemVerilog and HVL experience, and hands-on use of EDA tools to debug and verify complex digital systems. Collaborates across teams, automates processes, and contributes to the development of robust verification environments for Cadence’s advanced semiconductor software/hardware IP.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
2 years ago

Lead Product Validation Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Lead product verification engineer responsible for digital verification of SoC designs, requiring strong HDL knowledge (Verilog/VHDL), SystemVerilog and HVL experience, and hands-on use of EDA tools to debug and verify complex digital systems. Collaborates across teams, automates processes, and contributes to the development of robust verification environments for Cadence’s advanced semiconductor software/hardware IP.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance

Key Responsibilities

  • •Explain and implement design verification strategies for complex digital systems and SoC verification.
  • •Utilize HDL languages (Verilog/VHDL) and EDA tools to debug and verify designs, focusing on verification problems.
  • •Automate processes through scripting to improve verification efficiency and repeatability.
  • •Develop and maintain verification environments using SystemVerilog and UVM for robust validation.
  • •Collaborate with cross-functional teams to ensure verification coverage and alignment with product requirements.

Key Requirements

  • •Bachelor's degree (B.Tech/B.E./M.E./M.Tech) in Electrical/Electronics or Computer Science
  • •3-6 years of relevant experience in digital verification/SoC verification
  • •Strong understanding of HDLs (Verilog and/or VHDL) and experience with SystemVerilog
  • •Experience with EDA tools (Cadence or others) and debugging verification problems
  • •Experience with SystemVerilog, C++, UVM and functional verification of complex digital systems
Experience:3-6 yearsSemiconductorElectronicsSoC
Education:Bachelor's
Skills:CommunicationPresentationProblem-solving
Tech Stack:VerilogVHDLSystemVerilogC++UVMCadencePCIeUSB3/4

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor