Principal Digital Verification Engineer

Ciena
New York
Workplace: OnsiteFull timeUSD 147,100 - 234,900 annuallyFunction: Software EngineeringEducation: bachelorsSkills: ["SystemVerilog","UVM","SVA","Simulators","Python","Make","Bash","C","C++","Jira","Git"]

Expert digital verification engineer responsible for validating the Wavelogic digital blocks and subsystems for Ciena’s optical transmission products. Develop and implement verification strategies using SystemVerilog, UVM, and formal methods; create and optimize test environments, coverage plans, and verification test plans; mentor teammates and manage priorities; estimate schedules and report progress; collaborate with systems engineers and architects in Rochester, NY to ensure robust Serdes verification.

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FursaFursa
Ciena
Ciena
3 months ago

Principal Digital Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Expert digital verification engineer responsible for validating the Wavelogic digital blocks and subsystems for Ciena’s optical transmission products. Develop and implement verification strategies using SystemVerilog, UVM, and formal methods; create and optimize test environments, coverage plans, and verification test plans; mentor teammates and manage priorities; estimate schedules and report progress; collaborate with systems engineers and architects in Rochester, NY to ensure robust Serdes verification.
Location: New York
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •Understand architecture and functional requirements and collaborate with systems engineers and architects.
  • •Validate entire subsystems using simulation, formal, and coverage methods; ensure thorough verification coverage.
  • •Create, review, and optimize simulation environment components, test cases, functional coverage, and formal verification plans.
  • •Lead focused groups or mentor individuals and manage priorities to reach objectives.
  • •Estimate schedules and provide status updates; report to Senior Manager as needed.

Pay and Benefits

Salary: USD 147,100 - 234,900 annually
Equity and Bonus:Equity
Perks:Health Insurance401kEquityPaid Leave

Key Requirements

  • •Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with expert level experience in the use of System Verilog, UVM, SVA, and simulators from major vendors.
  • •Proven ability in determining appropriate and comprehensive digital verification and coverage strategies
  • •Highly motivated self-starter, able to work independently, while being a great teammate
  • •Ability to methodically address (debug) sophisticated technical problems.
  • •Excellent organization, written and oral English communication skills.
Experience:TelecommunicationsSemiconductorsDigital verification
Education:Bachelor's
Skills:SystemVerilogUVMSVASimulatorsPythonMakeBashCC++JiraGit
Languages:English
Tech Stack:SystemVerilogUVMSVASimulationJiraGitPythonMakeBashCC++

Company Brief

Ciena
Provides networking systems, software, and services that enable service providers, cloud operators, and enterprises to deliver high-capacity connectivity and adaptive network solutions worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Hanover, United States
Founded: 1992
Glassdoor
Glassdoor: 3.8
WebsiteLinkedIn