R&D Engineer IC Design

Broadcom
India
Full timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Communication","Interpersonal","Leadership","Debugging","Problem-solving"]

Join the Central Engineering Group as a memory design validation engineer, working on memory compilers and custom macros for SRAM, multi-ports, register files, TCAM, and ROM at 2nm and beyond. You’ll lead functional verification, root-cause issues, and signal integrity analysis, run transistor-level simulations for power-up/lock-up and timing margins, perform EM/IR checks, and automate verification with scripting tools. Coordinate with memory design and modeling leads to execute validation plans.

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FursaFursa
Broadcom
Broadcom
1 month ago

R&D Engineer IC Design

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Source: Company careers pageValidated by: Fursa AI
Last checked: 24 days agoStatus: Live
Reposted: similar role first listed 2 months ago

Job Summary

Join the Central Engineering Group as a memory design validation engineer, working on memory compilers and custom macros for SRAM, multi-ports, register files, TCAM, and ROM at 2nm and beyond. You’ll lead functional verification, root-cause issues, and signal integrity analysis, run transistor-level simulations for power-up/lock-up and timing margins, perform EM/IR checks, and automate verification with scripting tools. Coordinate with memory design and modeling leads to execute validation plans.
Location: India
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead memory design validation for SRAM, multi-ports, register files, TCAM, and ROM compilers and custom macros on 2nm and other cutting-edge process technologies.
  • •Perform functional verification and investigate/root-cause design discrepancies to resolve them.
  • •Run signal integrity analysis to identify design weaknesses and propose solutions.
  • •Conduct transistor-level simulations to check power-up/lock-up issues and validate timing and internal margins.
  • •Develop scripts to automate verification flow and data analysis, and support silicon debug with correlation to spice models.

Key Requirements

  • •5+ years of relevant experience and a Master in Electronics Engineering.
  • •Expertise in development of memory macros across architectures and types, including SRAM, multi-ports, register files, TCAM, and ROM.
  • •Strong understanding of transistor-level circuit behavior and analysis.
  • •Hands-on experience with transistor-level simulators and waveform viewer tools (e.g., HSPICE, Spectre, XA, PrimeSim, XARA, nWave).
  • •Experience with Cadence schematic/layout editor tools and scripting (Skill, Perl, Python).
Experience:5+ yearsSemiconductorIC designMemory systems
Education:Master's in Electronics Engineering
Skills:CommunicationInterpersonalLeadershipDebuggingProblem-solving
Tech Stack:CadenceHSPICESpectreXAPrimeSimXARANWaveSkillPerlPythonWaveform viewerMonte Carlo

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn