R&D Engineer IC Design

Join the Central Engineering Group as a memory design validation engineer, working on memory compilers and custom macros for SRAM, multi-ports, register files, TCAM, and ROM at 2nm and beyond. You’ll lead functional verification, root-cause issues, and signal integrity analysis, run transistor-level simulations for power-up/lock-up and timing margins, perform EM/IR checks, and automate verification with scripting tools. Coordinate with memory design and modeling leads to execute validation plans.