Staff Silicon Design Engineer

AMD
Penang
Workplace: HybridFull timeMYR 126,000 - 180,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8-10 yearsEducation: bachelorsSkills: ["Communication","Teamwork","Analytical thinking","Problem-solving"]

Drive front-end chip implementation across the silicon lifecycle, taking RTL code through design/implementation flow to deliver a netlist package for physical design. Develop and enhance ASIC design methodologies and flows, coordinate with EDA vendors, and perform CDC/lint, timing closure, lower-power implementation, and netlist quality checks in partnership with RTL and physical design teams. Apply AI/ML-enabled approaches to improve engineering productivity and development efficiency.

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FursaFursa
AMD
AMD
21 hours ago

Staff Silicon Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Drive front-end chip implementation across the silicon lifecycle, taking RTL code through design/implementation flow to deliver a netlist package for physical design. Develop and enhance ASIC design methodologies and flows, coordinate with EDA vendors, and perform CDC/lint, timing closure, lower-power implementation, and netlist quality checks in partnership with RTL and physical design teams. Apply AI/ML-enabled approaches to improve engineering productivity and development efficiency.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive front-end chip implementation from RTL through the design/implementation flow to netlist delivery for physical design.
  • •Develop and execute ASIC design methodology and flow development, including interfacing with EDA vendors on technology.
  • •Perform CDC/lint checks and support timing closure activities with RTL designers and the physical design (PD) team.
  • •Execute lower power implementation tasks and support netlist quality checks with RTL and PD teams.
  • •Improve engineering productivity, quality, and development efficiency across the silicon lifecycle using AI/ML-enabled approaches.

Pay and Benefits

Salary: MYR 126,000 - 180,000 annually

Key Requirements

  • •Experience with Verilog RTL design/implementation and large digital ASIC projects.
  • •Front-end EDA tool and flow experience (e.g., Design Compiler, PrimeTime, Conformal, VSI/VC-static, Formality).
  • •Experience with Unix/Linux and scripting (e.g., Tcl, Perl).
  • •Knowledge of CDC/lint, timing closure, and lower-power design methodology.
  • •Bachelors or Masters degree in Computer Engineering/Electrical & Electronics Engineering.
Experience:8-10 yearsASIC/SoC designDigital designEDA toolsFront-end ASICAI/ML for engineering workflows
Education:Bachelor's in Computer Engineering / Electrical & Electronics Engineering
Skills:CommunicationTeamworkAnalytical thinkingProblem-solving
Languages:En-us
Tech Stack:ASICSoCRTLVerilogCDC/lintTiming closureLower power designNetlistDesign CompilerPrimeTimeConformalVSI/VC-staticFormalityUnixLinuxTclPerlAI/ML

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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