Sr. RTL Design Engineer (Silicon Engineering)

SpaceX
Irvine, Austin, Sunnyvale, Redmond
Workplace: OnsiteFull time160,000 - 225,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","Python","EDAs","HDL tools","HDL simulators","HDL lint","Clock domain crossing","Power optimization","Bus protocols (AXI, AHB)"]

Lead RTL implementation for next-generation SpaceX ASICs used in Starlink satellites and ground systems. Collaborate with cross-disciplinary teams to design, verify, and bring up silicon, optimizing clock domains and power while enabling high-performance, space-grade semiconductor solutions for global connectivity.

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FursaFursa
SpaceX
SpaceX
3 months ago

Sr. RTL Design Engineer (Silicon Engineering)

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Last checked: 15 hours agoStatus: Live

Job Summary

Lead RTL implementation for next-generation SpaceX ASICs used in Starlink satellites and ground systems. Collaborate with cross-disciplinary teams to design, verify, and bring up silicon, optimizing clock domains and power while enabling high-performance, space-grade semiconductor solutions for global connectivity.
Location: Irvine, Austin, Sunnyvale, Redmond
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • •Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate top level and deliver verified, synthesis/timing clean design
  • •Work with verification team to ensure all aspects are covered and verified
  • •Provide timing constraints for IPs and support physical implementation (synthesis, timing closure, formality check)
  • •Participate in silicon bring-up and validation

Pay and Benefits

Salary: 160,000 - 225,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceVisionDental401kEquityParental LeavePaid Leave

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • •5+ years of experience in RTL implementation
  • •Experience with Verilog/SystemVerilog and RTL design
  • •ASIC/SoC system integration experience
  • •Experience with embedded CPU subsystems
Experience:5+ yearsAerospaceSpace
Education:Bachelor's
Skills:VerilogSystemVerilogRTLPythonEDAsHDL toolsHDL simulatorsHDL lintClock domain crossingPower optimizationBus protocols (AXI, AHB)
Languages:English
Tech Stack:VerilogSystemVerilogRTLPythonEDA toolsHDL simulatorsHDL LintAXIAHBASICSoC

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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