Sr. RTL Design Engineer (Silicon Engineering)
SpaceX
Irvine, Austin, Sunnyvale, Redmond
Workplace: OnsiteFull time160,000 - 225,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","Python","EDAs","HDL tools","HDL simulators","HDL lint","Clock domain crossing","Power optimization","Bus protocols (AXI, AHB)"]Lead RTL implementation for next-generation SpaceX ASICs used in Starlink satellites and ground systems. Collaborate with cross-disciplinary teams to design, verify, and bring up silicon, optimizing clock domains and power while enabling high-performance, space-grade semiconductor solutions for global connectivity.
