Modeling Architect

Neurophos
Austin, Sunnyvale
Workplace: OnsiteFull timeUSD 170,000 - 200,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 3+ yearsEducation: bachelorsSkills: ["Debugging","Collaboration","Documentation"]

Design and build hands-on architecture models for an optical AI inference accelerator, partnering with senior engineers across system/performance modeling and hardware block modeling. You’ll run and refine inference workloads, bind Hugging Face/PyTorch to the programming model, and co-design tiling, scheduling, ISA, and memory hierarchy. Own reproducible tests, configs, and plots, and drive C++/SystemVerilog generation and RTL simulation using Verilator.

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FursaFursa
Neurophos
Neurophos
2 days ago

Modeling Architect

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Design and build hands-on architecture models for an optical AI inference accelerator, partnering with senior engineers across system/performance modeling and hardware block modeling. You’ll run and refine inference workloads, bind Hugging Face/PyTorch to the programming model, and co-design tiling, scheduling, ISA, and memory hierarchy. Own reproducible tests, configs, and plots, and drive C++/SystemVerilog generation and RTL simulation using Verilator.
Location: Austin, Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Bring up inference workloads as they ship, including transformers and MoE models, prefill vs decode, KV cache, expert routing, quantization, and mapped retrieval/speech/vision/recommendation workloads.
  • •Bind Hugging Face and PyTorch workloads to the programming model and run them on the functional model.
  • •Co-design tiling, scheduling, the ISA, the SRAM and HBM hierarchy, and multi-chip mapping for the accelerator.
  • •Build modeling-stack layers including roofline/limiter studies, Python energy/latency models, C++ functional models, cycle-approximate performance/power models, and RTL simulation.
  • •Own tests, configs, and plots so results are rerunnable; review C++ and SystemVerilog generated via coding agents and share findings with design/compiler/runtime/RTL teams.

Pay and Benefits

Salary: USD 170,000 - 200,000 annually
Equity and Bonus:Equity
Perks:Health InsurancePaid Leave401kEquityDentalVisionLife

Key Requirements

  • •3+ years of experience in hardware modeling, performance simulation, computer architecture, or related work.
  • •Proficiency in Python or modern C++ (C++17 or later).
  • •Working knowledge of computer architecture and microarchitecture, including pipelines, caches, memory hierarchies, and ISA.
  • •Ability to convert an LLM/GEMM/accelerator paper into a workload config using Hugging Face or PyTorch.
  • •BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
Experience:3+ yearsHardware modelingPerformance simulationComputer architecture
Education:Bachelor's
Skills:DebuggingCollaborationDocumentation
Tech Stack:PythonC++C++17Hugging FacePyTorchHSASystemVerilogVerilogVerilatorSystemCGem5SSTRTL co-simulationEvent-driven simulationHBMDRAMSRAMNoCAXIDMA

Company Brief

Neurophos
Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Growth Stage Startup
Funding: Series A
Headquarters: Austin, United States
Founded: 2020
WebsiteLinkedIn