RTL Design Manager

AMD
Hyderabad
Workplace: OnsiteFull timeINR 4,086,670 - 5,838,100 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Leadership","Communication","Project planning","Technical stakeholder management","Team building"]

Lead the Front End SOC Design Team for next-generation Adaptable Compute Acceleration Platform devices. You’ll manage engineers delivering design and implementation of high-performance, low-power SoCs and SOC Chiplets, drive microarchitecture and RTL implementation, integrate IP, and ensure design quality for synthesis. You’ll also define/evolve IP/SOC design methodologies, run design reviews and tapeout checks, and improve team processes through automation and AI adoption.

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FursaFursa
AMD
AMD
2 days ago

RTL Design Manager

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Lead the Front End SOC Design Team for next-generation Adaptable Compute Acceleration Platform devices. You’ll manage engineers delivering design and implementation of high-performance, low-power SoCs and SOC Chiplets, drive microarchitecture and RTL implementation, integrate IP, and ensure design quality for synthesis. You’ll also define/evolve IP/SOC design methodologies, run design reviews and tapeout checks, and improve team processes through automation and AI adoption.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Manage the Front End SOC Design Team, including hiring, coaching, reviewing, and retaining engineers.
  • •Plan and track project execution, reporting key metrics and ensuring delivery from microarchitecture through timing closure.
  • •Lead design reviews for features and quality, participate in tapeout checklists and reviews, and ensure design readiness for synthesis.
  • •Integrate RTL functions and IP from internal and external sources, and ensure quality and execution throughout design.
  • •Define/evolve IP/SOC design methodologies and improve team processes using AI adoption and traditional automation.

Pay and Benefits

Salary: INR 4,086,670 - 5,838,100 annually

Key Requirements

  • •12+ years of experience in digital engineering with RTL design background.
  • •Engineering digital design experience with RTL design in Verilog/SystemVerilog.
  • •Solid understanding of DFT technologies and experience executing DFT flows.
  • •Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, and VCS simulation.
  • •Experience specifying timing constraints for multiple clock domains/modes and designing with multiple power domains using UPF.
Experience:12+ yearsSOC/ASIC design
Education:Bachelor's in Electrical Engineering
Skills:LeadershipCommunicationProject planningTechnical stakeholder managementTeam building
Languages:English
Tech Stack:RTLVerilogSystemVerilogDFTSpyglassQuesta CDCCadence ConformalVCS simulationSynopsys Design CompilerPrimetimeUPFTCLPythonPerlPerforceIC ManageGitLinuxWindows

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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