Lead IP Verification Engineer

AMD
San Jose
Workplace: HybridFull timeFunction: Administration & Executive AssistanceEducation: bachelorsSkills: ["Technical leadership","Mentoring","Communication","Problem-solving","Detail-oriented","Analytical skills","Collaboration","Continuous learning"]

Develop and architect UVM-based IP verification environments for PCIe and CXL-based FPGA/ASIC solutions, collaborating across architecture, IP design, physical design, firmware, and product engineering. Build verification plans covering feature interactions and performance needs, then create directed and constrained-random tests, run regressions, and debug failures to ensure first-pass silicon success. Drive verification automation and methodology improvements, including adoption of AI-assisted tools, to boost efficiency and coverage.

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FursaFursa
AMD
AMD
1 day ago

Lead IP Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 40 minutes agoStatus: Live

Job Summary

Develop and architect UVM-based IP verification environments for PCIe and CXL-based FPGA/ASIC solutions, collaborating across architecture, IP design, physical design, firmware, and product engineering. Build verification plans covering feature interactions and performance needs, then create directed and constrained-random tests, run regressions, and debug failures to ensure first-pass silicon success. Drive verification automation and methodology improvements, including adoption of AI-assisted tools, to boost efficiency and coverage.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Architect and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable components.
  • •Collaborate with architects and hardware/firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
  • •Develop verification plans covering feature interactions, hardware/software integration, performance requirements, and system-level use cases.
  • •Create directed and constrained-random tests, run regressions, and debug failures to ensure high functional coverage and design quality.
  • •Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve efficiency and productivity.

Key Requirements

  • •ASIC/IP verification experience using UVM methodology.
  • •Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
  • •Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
  • •Proficiency in scripting and automation using Python, Perl, or similar languages.
  • •Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience:ASIC/FPGA developmentHigh-speed protocolsDigital designSystem-level design
Education:Bachelor's in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Skills:Technical leadershipMentoringCommunicationProblem-solvingDetail-orientedAnalytical skillsCollaborationContinuous learning
Languages:En-us
Tech Stack:UVMSystemVerilogVerilogPCIeCXLEthernetPythonPerl

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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