ASIC Physical Design Engineer
San Jose, Austin
Workplace: OnsiteFull timeUSD 167,700 - 245,200 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Cross-team collaboration","Debugging","Methodology improvement","Timing analysis","Quality focus"]Own RTL-to-GDSII physical implementation for advanced semiconductor nodes supporting Cisco Silicon One networking chips. Drive hierarchical floorplanning, place-and-route, clock/power distribution, and timing convergence, including STA sign-offs and automated STA scripting. Use Prime Closure/PrimeTime to implement and manage ECO timing strategies, analyze quality/efficiency gaps, and collaborate with RTL, DFT, EDA vendors, and tool owners to improve design flow and methodology alignment.
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