ASIC Physical Design Engineer

Cisco
San Jose, Austin
Workplace: OnsiteFull timeUSD 167,700 - 245,200 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Cross-team collaboration","Debugging","Methodology improvement","Timing analysis","Quality focus"]

Own RTL-to-GDSII physical implementation for advanced semiconductor nodes supporting Cisco Silicon One networking chips. Drive hierarchical floorplanning, place-and-route, clock/power distribution, and timing convergence, including STA sign-offs and automated STA scripting. Use Prime Closure/PrimeTime to implement and manage ECO timing strategies, analyze quality/efficiency gaps, and collaborate with RTL, DFT, EDA vendors, and tool owners to improve design flow and methodology alignment.

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FursaFursa
Cisco
Cisco
4 hours ago

ASIC Physical Design Engineer

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Job Summary

Own RTL-to-GDSII physical implementation for advanced semiconductor nodes supporting Cisco Silicon One networking chips. Drive hierarchical floorplanning, place-and-route, clock/power distribution, and timing convergence, including STA sign-offs and automated STA scripting. Use Prime Closure/PrimeTime to implement and manage ECO timing strategies, analyze quality/efficiency gaps, and collaborate with RTL, DFT, EDA vendors, and tool owners to improve design flow and methodology alignment.
Location: San Jose, Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own and drive RTL-to-GDSII implementation for advanced ASIC nodes (sub-16nm to 2nm).
  • •Define and execute hierarchical floorplanning, place and route, clock and power distribution, and timing convergence strategies.
  • •Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated STA scripts within STA tools.
  • •Implement and manage timing ECO strategies using Prime Closure/PrimeTime and develop creative debugging solutions.
  • •Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency and align best practices across projects.

Pay and Benefits

Salary: USD 167,700 - 245,200 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid ParentalLong-term DisabilityBasic LifeRsusPaid LeaveAnnual Bonus

Key Requirements

  • •Bachelor’s degree in Electrical Engineering plus 5+ years (or Master’s in Electrical Engineering plus 2+ years, or PhD plus 0+ years).
  • •Hands-on experience in ASIC physical design and implementation.
  • •Experience with hierarchical floorplanning, clock and power distribution, global signal/I/O planning, physical convergence, timing closure, and hierarchical design methodology.
  • •Experience with power integrity analysis and designs >100M gates in advanced nodes (16nm, 14nm, 7nm, 5nm, 3nm, 2nm).
  • •Ability to perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs.
Experience:5+ yearsSemiconductorsASIC designEDANetworking hardwareRTL-to-GDSIIAdvanced nodes
Education:Bachelor's in Electrical Engineering
Skills:Cross-team collaborationDebuggingMethodology improvementTiming analysisQuality focus
Tech Stack:RTLGDSIIStatic timing analysis (STA)Prime ClosurePrimeTimePrimeTime-DMSATCLPythonCadence InnovusSynopsys FCCadence GenusSynopsys FormalityCadence LECApache RedhawkVoltusSynopsys ICVMentor CalibreAI tools

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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