Senior Digital Design Engineer, HBM

Micron Technology
United States
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Communication","Documentation","Collaboration","Analytical thinking"]

Drive the end-to-end digital design flow for HBM, from concept definition and specification through RTL implementation, verification support, documentation, and post-silicon debug. Build scalable, parameterized RTL in Verilog/SystemVerilog, define digital micro-architecture (FSMs, datapaths, FIFOs, pipelines, arbitration), and analyze area/power/latency tradeoffs. Perform CDC/RDC and clock/reset strategy work, support synthesis and static timing (SDC), apply low-power methods (CPF/UPF), and collaborate with verification, DFT, physical design, and CAD teams for design closure.

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FursaFursa
Micron Technology
Micron Technology
4 weeks ago

Senior Digital Design Engineer, HBM

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Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live

Job Summary

Drive the end-to-end digital design flow for HBM, from concept definition and specification through RTL implementation, verification support, documentation, and post-silicon debug. Build scalable, parameterized RTL in Verilog/SystemVerilog, define digital micro-architecture (FSMs, datapaths, FIFOs, pipelines, arbitration), and analyze area/power/latency tradeoffs. Perform CDC/RDC and clock/reset strategy work, support synthesis and static timing (SDC), apply low-power methods (CPF/UPF), and collaborate with verification, DFT, physical design, and CAD teams for design closure.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive all stages of the digital design flow, including concept definition, specification, RTL implementation, verification support, documentation, and post-silicon debug.
  • •Develop high-quality RTL in Verilog/SystemVerilog using scalable, parameterized design techniques aligned to architectural specifications.
  • •Define and refine micro-architecture for digital logic blocks such as FSMs, datapaths, FIFOs, pipelines, and arbitration logic.
  • •Analyze tradeoffs across area, power, latency, and throughput and document design decisions.
  • •Apply CDC/RDC analysis, clocking/reset strategies, low-power methodologies (CPF/UPF, clock gating), and collaborate with verification/DFT/physical design/CAD teams to achieve robust design closure.

Pay and Benefits

Perks:Health InsuranceDentalVisionPaid LeavePaid HolidaysParental Leave

Key Requirements

  • •Develop RTL in Verilog/SystemVerilog using scalable, parameterized design techniques aligned to architectural specifications.
  • •Define and refine micro-architecture for digital logic blocks, including FSMs, datapaths, FIFOs, pipelines, and arbitration logic.
  • •Analyze tradeoffs across area, power, latency, and throughput and clearly document design decisions.
  • •Perform CDC/RDC analysis and apply sound clocking and reset strategies, including identifying early timing challenges.
  • •Support synthesis and static timing analysis by creating/debugging SDC constraints and interpreting timing reports.
Experience:SemiconductorHBMRTL designVerificationLow-power design
Skills:CommunicationDocumentationCollaborationAnalytical thinking
Tech Stack:VerilogSystemVerilogRTLAI-Enabled toolsCDCRDCSDCStatic timing analysisSynthesisCPFUPFClock gatingFSMDatapathsFIFOsPipelinesArbitration logicCDC/RDC analysisCPF/UPFMulti-domain partitioning

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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