Senior ASIC Design Engineer – Clocks IP

NVIDIA
Santa Clara, Austin
Workplace: HybridFull timeUSD 136,000 - 264,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Interpersonal skills","Collaboration","Problem-solving"]

Join NVIDIA’s Clocks team to architect GPU/CPU clock domains and design clocking topologies that meet functional, physical, and test requirements. Partner across front-end design, physical design/timing, verification, and DFT teams to deliver clock RTL, improve PPA through RTL and power/timing trade-offs, and support end-to-end ASIC execution through silicon bring-up and lab debugging.

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FursaFursa
NVIDIA
NVIDIA
5 days ago

Senior ASIC Design Engineer – Clocks IP

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Last checked: 21 hours agoStatus: Live

Job Summary

Join NVIDIA’s Clocks team to architect GPU/CPU clock domains and design clocking topologies that meet functional, physical, and test requirements. Partner across front-end design, physical design/timing, verification, and DFT teams to deliver clock RTL, improve PPA through RTL and power/timing trade-offs, and support end-to-end ASIC execution through silicon bring-up and lab debugging.
Location: Santa Clara, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Architect the clock domain to satisfy functional, physical, and testing design requirements.
  • •Design GPU or CPU clocks across architectural, design, and physical constraints while collaborating with multiple teams.
  • •Improve chip power, performance, and area (PPA) by evaluating trade-offs across DFx, physical implementation, power optimization, and timing closure; implement clocking topologies in RTL.
  • •Collaborate with physical design and timing teams to address clocking concerns and support high-speed clocking.
  • •Deliver clock RTL information to GPU, CPU, SoC verification, timing, and DFT teams and participate through silicon bring-up and lab triage of silicon/programming bugs.

Pay and Benefits

Salary: USD 136,000 - 264,500 annually
Equity and Bonus:Equity

Key Requirements

  • •BS in Electrical Engineering or equivalent experience (MS preferred).
  • •3+ years of relevant work experience.
  • •Deep understanding of logic optimization techniques and power/performance/area (PPA) trade-offs.
  • •Experience in RTL design (Verilog), verification, and logic synthesis.
  • •Strong coding skills in Python or other industry-standard scripting languages.
Experience:3+ years
Education:Bachelor's in Electrical Engineering
Skills:Interpersonal skillsCollaborationProblem-solving
Tech Stack:ASICClocksClock domainRTLVerilogLogic synthesisVerificationDFxPythonScriptingDFTMicro-archFloor-planningPhysical implementationPower optimization

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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