New Graduate Engineer, Silicon Engineering

SpaceX
Irvine, Palo Alto, Redmond
Workplace: OnsiteFull timeUSD 135,000 - 210,000 annuallyFunction: Hardware, Embedded & Systems EngineeringSkills: ["Hands-on execution","Self-starter","Collaboration","Problem solving"]

Develop next-generation silicon for SpaceX’s Starlink program across pre-silicon to post-silicon. Work on ASIC/FPGA design and verification, RF/Analog IC simulation and modeling, RF/microwave circuit development, and DSP-oriented RTL design in SystemVerilog. Participate in lab bring-up and validation, physical design and signoff steps, and advanced technology tapeouts. Ideal for hands-on new graduates ready to execute full design/verification workflows.

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FursaFursa
SpaceX
SpaceX
21 hours ago

New Graduate Engineer, Silicon Engineering

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Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live

Job Summary

Develop next-generation silicon for SpaceX’s Starlink program across pre-silicon to post-silicon. Work on ASIC/FPGA design and verification, RF/Analog IC simulation and modeling, RF/microwave circuit development, and DSP-oriented RTL design in SystemVerilog. Participate in lab bring-up and validation, physical design and signoff steps, and advanced technology tapeouts. Ideal for hands-on new graduates ready to execute full design/verification workflows.
Location: Irvine, Palo Alto, Redmond
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Entry level

Key Responsibilities

  • •Participate in all phases of ASIC/FPGA design and verification, including RTL implementation/verification and emulation.
  • •Bring up and validate ASICs and FPGAs in the lab, including writing embedded software using C/C++ and/or Python.
  • •Simulate and model RFIC systems, derive specifications for RFIC subsystems/circuits, and develop RF/microwave circuits in SiGe or CMOS processes.
  • •Perform physical design steps such as synthesis, floor planning, place and route, timing/noise analysis, and signoff checks.
  • •Develop DSP-focused RTL in SystemVerilog, verify against fixed-point MATLAB models, and support silicon tapeouts for future Starlink SOCs.

Pay and Benefits

Salary: USD 135,000 - 210,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceVisionDental401kPaid ParentalPaid Leave

Key Requirements

  • •Graduating with a bachelor’s degree, master’s degree, or PhD in 2026 or 2027.
  • •Bachelor’s degree in an engineering discipline, mathematics, or physics.
  • •Experience working with ASIC, SoC, FPGA, RFIC, or MMIC.
  • •Experience with analog/digital CMOS integrated circuit design and/or physical design.
  • •Experience with SystemVerilog/Verilog/VHDL and/or C/C++ plus scripting/automation (e.g., Python).
Skills:Hands-on executionSelf-starterCollaborationProblem solving
Languages:English
Tech Stack:ASICSoCFPGARFICMMICSystemVerilogVerilogVHDLC/C++PythonMATLABADSSpectreHFSSMomentumSiGeCMOS

Eligibility

Nationality:US National
Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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