Packaging Design Engineer

AMD
San Jose, San Diego
Workplace: HybridFull timeUSD 200,000 - 300,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Collaboration","Mentoring"]

Design and optimize FPGA package solutions by translating electrical requirements into cost-effective, manufacturable package technologies. Partner with chip, technology, and systems teams through pre-design negotiations to design signoff. Use Cadence for design and simulation, develop high-bandwidth multi-signal models, run routing/stack-up/placement studies, perform power integrity and PDN requirement work, and support model-to-measurement correlation and tooling via scripts.

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FursaFursa
AMD
AMD
1 day ago

Packaging Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live

Job Summary

Design and optimize FPGA package solutions by translating electrical requirements into cost-effective, manufacturable package technologies. Partner with chip, technology, and systems teams through pre-design negotiations to design signoff. Use Cadence for design and simulation, develop high-bandwidth multi-signal models, run routing/stack-up/placement studies, perform power integrity and PDN requirement work, and support model-to-measurement correlation and tooling via scripts.
Location: San Jose, San Diego
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Use Cadence tools for package design, modeling, and simulations, and drive designs from pre-design negotiations through signoff.
  • •Define package/module design requirements (technology, stack-up) using analytical and simulation tools and negotiate product specifications with chip/system teams.
  • •Conduct routing, stack-up, and component placement studies; translate design guidelines, technology, stack-up, and manufacturing time requirements for device packaging.
  • •Develop multi-signal package/module models over 50 GHz bandwidth and create test structures to support model-to-measurement correlation.
  • •Perform Power Integrity analysis and develop power delivery network (PDN) requirements; build scripts and maintain design guideline/rules databases.

Pay and Benefits

Salary: USD 200,000 - 300,000 annually

Key Requirements

  • •Translate electrical requirements into package technology requirements that are cost-effective and manufacturable.
  • •Current working knowledge of Cadence package design tools; SKILL knowledge is a plus.
  • •Understand organic/PCB technologies to interpret and negotiate layout guidelines.
  • •Working knowledge of 2D/3D package design and modeling tools such as Cadence, Ansys, and AutoCAD.
  • •Knowledge of SerDes design and package/PCB layout constraints; DoE and DFM/DFR knowledge is a plus.
Education:Bachelor's
Skills:CommunicationCollaborationMentoring
Tech Stack:CadenceSKILLAnsysAutoCADPCB layoutPower Integrity analysis

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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