Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsSkills: ["Cross-functional collaboration","Design rule management","Electrical simulation","Reliability-focused thinking","Process coordination"]

Drive advanced packaging build enablement for High Bandwidth Memory (HBM) programs, bridging silicon design and packaging requirements. You will build and tapeout PWF reticle designs, develop DFTs for packaging-related fail modes, coordinate test structure creation, manage design/process rules, and engage on BEOL/TSV design. The role also includes DFMEA maintenance and electrical simulations to understand fail-mode mechanisms, partnering across global design, process, assembly, test, and marketing teams.

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FursaFursa
Micron Technology
Micron Technology
3 months ago

Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live

Job Summary

Drive advanced packaging build enablement for High Bandwidth Memory (HBM) programs, bridging silicon design and packaging requirements. You will build and tapeout PWF reticle designs, develop DFTs for packaging-related fail modes, coordinate test structure creation, manage design/process rules, and engage on BEOL/TSV design. The role also includes DFMEA maintenance and electrical simulations to understand fail-mode mechanisms, partnering across global design, process, assembly, test, and marketing teams.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Build and tapeout PWF reticle designs for advanced packaging.
  • •Develop DFTs in test vehicles for packaging-related fail modes.
  • •Coordinate with HIG-HBM DTPCO and HIG-HBM teams to build test structures for live die.
  • •Manage design rules and process design rules for PWF, wafer thinning/dicing, die stacking, and related steps.
  • •Engage on BEOL and TSV design efforts; maintain DFMEA for packaging process steps and perform electrical simulations to understand fail-mode mechanisms.

Key Requirements

  • •5+ years of experience in die design and physical layout engineering.
  • •Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent).
  • •Proven experience with TSV-based die design, including KOZ management, micro-bump layout, and backside RDL.
  • •Deep expertise in physical design and layout using EDA tools such as Cadence Virtuoso, Innovus, Mentor Calibre, and Synopsys IC Compiler.
  • •Masters or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
Experience:5+ yearsSemiconductorHBM3D-ICAdvanced packagingMemoryEDATSVDFTHigh-speed memory interfaces
Education:
Skills:Cross-functional collaborationDesign rule managementElectrical simulationReliability-focused thinkingProcess coordination
Tech Stack:Cadence VirtuosoInnovusMentor CalibreSynopsys IC CompilerDFTDaisy chainsBISTBoundary scanIEEE P1838JEDEC HBM2EJEDEC HBM3JEDEC HBM3EDRCLVSERCPDKTSV designMicro-bump layoutBackside RDLDFMEA

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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Glassdoor: 3.7
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