Design Verification Engineer
AMD
Santa Clara
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["SystemVerilog","UVM","Python","Tcl","Make","PCIe","AXI","Ethernet","DDR","DMA","VCS","Verdi","DVE"]Design Verification Engineer to develop UVM-based verification environments for high-performance ASICs, driving verification closure across IP, subsystem and SoC, with hands-on SystemVerilog, testbench development, and cross-functional collaboration in a data-center networking context.

