SDC, Synthesis and STA Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 6-8 yearsEducation: bachelorsSkills: ["Collaboration","Debugging","Planning","Technical leadership"]

Own front-end implementation of IPs by planning and executing SDC development and IP closure. Drive SDC generation, verification, promotion/demotion, and equivalence checking using third-party or self-built tools, and support synthesis, LEC, CLP, and pre-/post-layout STA and timing closure as needed. Partner with design and PNR teams to meet schedule, ensure quality for synthesis/timing closure, and debug technical issues. Guide team members on technical topics.

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FursaFursa
AMD
AMD
1 week ago

SDC, Synthesis and STA Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 51 minutes agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Own front-end implementation of IPs by planning and executing SDC development and IP closure. Drive SDC generation, verification, promotion/demotion, and equivalence checking using third-party or self-built tools, and support synthesis, LEC, CLP, and pre-/post-layout STA and timing closure as needed. Partner with design and PNR teams to meet schedule, ensure quality for synthesis/timing closure, and debug technical issues. Guide team members on technical topics.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Plan and execute front-end implementation of IPs and closure.
  • •Own SDC development, including SDC generation, verification, promotion/demotion, and equivalence checking using third-party or self-built tools.
  • •Support front-end implementation activities such as synthesis, LEC, CLP, prelayout STA, and postlayout STA/timing closure as needed.
  • •Coordinate with design and PNR teams to achieve closure and complete delivery per schedule.
  • •Debug and resolve technical issues and guide team members on technical topics.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •Bachelors with 8 years of experience or Masters with 6 years of experience in Electrical Engineering.
  • •Develop SDC/constraints for designs, with or without using tools such as fisthail, excellicon, or TCM.
  • •Experience in synthesis, LEC, CLP, and STA/timing closure.
  • •Handle blocks with complex designs, high-frequency clocks, and complex clocking, with strong understanding of timing constraints, low power concepts, and DFT.
  • •Debug and resolve technical issues; scripting and automation interest is a plus.
Experience:6-8 years
Education:Bachelor's in Electrical Engineering
Skills:CollaborationDebuggingPlanningTechnical leadership
Tech Stack:SDCSynthesisSTAStatic timing analysisLECCLPTiming closureTiming constraintsLow powerDFTEquivalence checkingLintCDCRTLNetlistFisthailExcelliconTCM

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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