Sr. Staff Firmware Engineer (Secure Boot & Real Time Platform)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Design and implement a mission-critical secure boot chain, flash partition architecture, and hardware-enforced isolation for a software-defined vehicle platform. Own secure multi-stage boot flows (mask ROM through bootloaders), atomic A/B update layouts, and low-level state machines for partition switching and fallback. Build high-performance inter-core communication and fault-tolerant storage solutions to deliver zero-downtime, fail-safe robustness for autonomous systems.

Location: Sunnyvale, San Francisco

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Architect the secure boot chain by designing and optimizing a multi-stage secure boot sequence from immutable mask ROM through bootloaders to ensure execution integrity.
•Implement hardware-enforced isolation using hardware firewall technologies (e.g., NXP xRDC/XRDC4) and core-level MPUs.
•Manage cohort/domain IDs and resource controllers (MDAC, PAC) to enforce strict resource isolation, peripheral partitioning, and fault domain segregation.
•Implement fail-safe atomic A/B firmware update layouts using dual-bank partition architectures for robust slot updates.
•Design low-level state machines for partition switching, background flashing, and automatic runtime fallback loops.

Pay and Benefits

Salary: USD 189,240 - 266,760

Key Requirements

•Configure hardware-based cryptographic enclaves (HSMs, TPMs, or ARM TrustZone) for a hardware root of trust.
•Develop firmware controls for secure key storage, device attestation, and anti-rollback protection using eFuses or secure flash memory.
•Design and optimize low-latency inter-process/inter-core communication (IPC/ICC) using shared memory, hardware semaphores, and zero-copy data paths.
•Package and deploy low-level block drivers and fault-tolerant flash file systems (e.g., eMMC, UFS, QSPI).
•Implement advanced wear-leveling and delta compression techniques to maximize flash lifespan and minimize bus bandwidth.

Experience:Embedded systemsFirmware securitySoftware-defined vehiclesAutomotive

Tech Stack:Embedded CSecure bootMask ROMPrimary Bootloader (PBL)Secondary Bootloaders (SBL)U-BootNXP xRDCXRDC4Memory Protection Units (MPUs)Cohort/Domain IDsMaster Domain Assignment Controllers (MDAC)Peripheral Access Controllers (PAC)A/B firmware updatesHardware firewallInter-Process Communication (IPC)Inter-Core Communication (ICC)Shared memoryHardware semaphoresZero-copy data pathsHardware cryptographic enclaves

Company Brief

42dot

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42dot

1 month ago

Sr. Staff Firmware Engineer (Secure Boot & Real Time Platform)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: Sunnyvale, San Francisco

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Architect the secure boot chain by designing and optimizing a multi-stage secure boot sequence from immutable mask ROM through bootloaders to ensure execution integrity.
•Implement hardware-enforced isolation using hardware firewall technologies (e.g., NXP xRDC/XRDC4) and core-level MPUs.
•Manage cohort/domain IDs and resource controllers (MDAC, PAC) to enforce strict resource isolation, peripheral partitioning, and fault domain segregation.
•Implement fail-safe atomic A/B firmware update layouts using dual-bank partition architectures for robust slot updates.
•Design low-level state machines for partition switching, background flashing, and automatic runtime fallback loops.

Pay and Benefits

Salary: USD 189,240 - 266,760

Key Requirements

•Configure hardware-based cryptographic enclaves (HSMs, TPMs, or ARM TrustZone) for a hardware root of trust.
•Develop firmware controls for secure key storage, device attestation, and anti-rollback protection using eFuses or secure flash memory.
•Design and optimize low-latency inter-process/inter-core communication (IPC/ICC) using shared memory, hardware semaphores, and zero-copy data paths.
•Package and deploy low-level block drivers and fault-tolerant flash file systems (e.g., eMMC, UFS, QSPI).
•Implement advanced wear-leveling and delta compression techniques to maximize flash lifespan and minimize bus bandwidth.

Experience:Embedded systemsFirmware securitySoftware-defined vehiclesAutomotive

Company Brief

42dot

Website