SoC Digital Design Engineer, Multimedia Lab

Build and scale video codec hardware solutions by designing SoC top-level or subsystem architectures for NoC/CPU/NPU/ISP/Codec. Implement RTL in Verilog/SystemVerilog, run lint and clock/reset domain crossing checks, and collaborate across verification and backend teams to drive coverage closure, synthesis, SDC generation, STA, and power optimization. Contribute to low-power strategies using clock/power gating and the UPF flow for advanced process-node tape-outs.