Lead Design Engineer
Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 114,800 - 213,200 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Python","JIRA","Data visualization"]Lead electrical and functional validation for next-generation DDR interfaces (DDR5/LPDDR5/LPDDR6/HBM4/GDDR7); design testing strategies to accelerate post-silicon bring-up; transform raw data into actionable insights; drive cross-team debug workflows; deliver characterization reports influencing product decisions; automate validation and reporting with Python; serve as the go-to expert for customer DDR IP challenges.

