Physical Design Leader

Lead AMD’s Physical Design implementation for complex tiles within the CT India physical design team, working with SOC and PD/STA engineers to achieve first-pass silicon success. Drive backend PnR implementation and convergence activities from RTL through GDS, including signoff, physical verification, timing convergence, and IP integration. Manage and guide silicon design engineers delivering project tape-outs, collaborating cross-functionally to improve PPA and strengthen closure methodologies, including 3D die stacking execution.