CPU Physical Design Engineer

Intel
Austin
Workplace: OnsiteFull timeUSD 105,650 - 149,150 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: []

Join Intel’s CPU development team to implement custom CPU designs from RTL through GDS, building a manufacturing-ready design database. Own the end-to-end physical design flow—synthesis, place and route, CTS, floorplanning, and static timing/power/clock distribution—then perform verification and signoff including formal equivalence, DRC/LVS, noise, and power integrity. Collaborate with logic, circuit, architecture, and EDA automation teams to optimize power, frequency, and area.

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Intel
Intel
5 days ago

CPU Physical Design Engineer

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Last checked: 9 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Join Intel’s CPU development team to implement custom CPU designs from RTL through GDS, building a manufacturing-ready design database. Own the end-to-end physical design flow—synthesis, place and route, CTS, floorplanning, and static timing/power/clock distribution—then perform verification and signoff including formal equivalence, DRC/LVS, noise, and power integrity. Collaborate with logic, circuit, architecture, and EDA automation teams to optimize power, frequency, and area.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Perform physical design implementation of custom CPU designs from RTL to GDS to create a manufacturing-ready design database.
  • •Execute the CPU physical design flow including synthesis, place and route, clock tree synthesis, floorplanning, static timing analysis, and power/clock distribution.
  • •Drive verification and signoff activities such as formal equivalence verification, reliability verification, power integrity checks, layout verification, electrical rule checking, and structural design checking.
  • •Use CPU physical design expertise (e.g., physical clock design, timing closure, structured placement/routing, multi-power-domain analysis, and DFT-related activities).
  • •Partner with logic, circuit, architecture, and design automation teams and industry EDA vendors to improve tool capabilities, methodologies, and flow automation; optimize power, frequency, and area.

Pay and Benefits

Salary: USD 105,650 - 149,150 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •B.S. in Computer Engineering or Electrical Engineering (or related) with 2+ years of relevant experience, or M.S. with 1+ years of relevant experience.
  • •1+ years of experience in synthesis of a digital logic block or partition.
  • •1+ years experience with integrated circuit design tools (e.g., Synopsys/Cadence) including logic synthesis, place and route, and static timing analysis.
  • •1+ years experience in PV convergence (static timing and power analysis) and chip physical design verification including formal equivalence and DRC/LVS.
  • •Experience with TCL scripting and CPU physical design verification/signoff (including noise and power integrity).
Experience:1+ yearsSemiconductorsChip designCPU physical design
Education:Bachelor's in Computer Engineering or Electrical Engineering (or related)
Tech Stack:SynopsysCadenceRTL to GDSSynthesisPlace and routeClock tree synthesisFloor planningStatic timing analysisStatic timingPower and clock distributionPower integrityReliability verificationPower noise analysisFormal equivalence verificationLayout verificationElectrical rule checkingDRC/LVSTCL scriptingPV convergenceDFT

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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