Staff Silicon Design Engineer

AMD
Penang
Workplace: HybridFull timeMYR 126,000 - 180,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8-10 yearsSkills: ["Communication","Collaboration","Analytical thinking","Problem-solving","Teamwork"]

Drive front-end chip implementation for next-generation silicon development, taking RTL code through to a netlist package ready for physical design. Develop and improve ASIC design methodologies and flows, interfacing with EDA vendors and ensuring CDC/lint, timing closure, lower-power implementation, and netlist quality checks. Collaborate with RTL designers and the physical design team, with strong support for automation and engineering-productivity improvements.

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FursaFursa
AMD
AMD
17 hours ago

Staff Silicon Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Drive front-end chip implementation for next-generation silicon development, taking RTL code through to a netlist package ready for physical design. Develop and improve ASIC design methodologies and flows, interfacing with EDA vendors and ensuring CDC/lint, timing closure, lower-power implementation, and netlist quality checks. Collaborate with RTL designers and the physical design team, with strong support for automation and engineering-productivity improvements.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own front-end chip implementation, executing the flow from RTL to delivery of a netlist package ready for physical design.
  • •Develop ASIC design methodology and flow improvements, including interfacing with EDA vendors for technology support.
  • •Execute and validate CDC/lint, timing closure, lower power implementation, and netlist quality checks with RTL and PD teams.
  • •Collaborate cross-site with engineers across different locations and time zones.
  • •Contribute to engineering productivity and development efficiency across the silicon lifecycle, including AI/ML-based workflow improvements.

Pay and Benefits

Salary: MYR 126,000 - 180,000 annually

Key Requirements

  • •8–10 years of experience in ASIC/SoC front-end design and verification, including RTL implementation and verification.
  • •Experience with Verilog RTL design/implementation on large digital ASIC projects.
  • •Hands-on experience with front-end EDA tools and flows such as Design Compiler, PrimeTime, Conformal, VSI/VC-static, and Formality.
  • •Experience with Unix/Linux and scripting (Tcl, Perl).
  • •Knowledge of CDC/lint, timing closure, lower-power implementation, and netlist quality checks; physical design experience is a plus.
Experience:8-10 yearsASIC/SoCDigital design
Education:
Skills:CommunicationCollaborationAnalytical thinkingProblem-solvingTeamwork
Languages:En-us
Tech Stack:ASICSoCRTLVerilogDesign compilerPrimeTimeConformalVSI/VC-staticFormalityUnixLinuxTclPerlSynthesisPhysical designCdc/lintTiming closureLower power

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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