2 months ago

Software Engineer I: VIP

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Join Cadence's memory verification team in Belo Horizonte as a Software Engineer I: VIP. You will test and validate memory device models, collaborate with R&D to implement features for next-generation Verification IP tools, troubleshoot complex verification issues, and support customers through issue reproduction and resolution, while building strong relationships with peers and management in a fast-paced, globally connected environment.

Location: Belo Horizonte

Workplace: Hybrid

Employment Type: Full time

Job Function: Software Engineering

Seniority: Entry level

Key Responsibilities

•Test, validate, and deploy enhancements on memory device models for key customers.
•Collaborate with R&D to develop, implement, and test features for the next generation of Verification IP tools.
•Troubleshoot and resolve complex technical issues related to memory verification, including simulation failures, coverage gaps and performance bottlenecks.
•Provide clear and concise explanations of technical concepts and solutions to customers with varying levels of expertise.
•Support customer project needs including reproducing and fixing issues in-house to facilitate debugging and resolution.

Key Requirements

•Complete bachelor’s in computer science or computer Engineering or equivalent experience.
•Experience with Software development: 2 years
•Knowledge and experience with Object-oriented programming.
•Solid advanced data structures and algorithms knowledge.
•Knowledge of C/C++ programming language.

Experience:2-2 yearsMemory verificationVerification IPVIPMemory modelsEmbedded systems

Education:Bachelor's

Skills:CC++UnixObject-oriented programmingVerilogVHDLSV/UVMPythonTcl

Languages:EnglishPortuguese

Tech Stack:CC++UnixSV/UVMVerilogVHDLPythonTclDDRLPDDRHBMGDDR

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

2 months ago

Software Engineer I: VIP

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Belo Horizonte

Workplace: Hybrid

Employment Type: Full time

Job Function: Software Engineering

Seniority: Entry level

Key Responsibilities

•Test, validate, and deploy enhancements on memory device models for key customers.
•Collaborate with R&D to develop, implement, and test features for the next generation of Verification IP tools.
•Troubleshoot and resolve complex technical issues related to memory verification, including simulation failures, coverage gaps and performance bottlenecks.
•Provide clear and concise explanations of technical concepts and solutions to customers with varying levels of expertise.
•Support customer project needs including reproducing and fixing issues in-house to facilitate debugging and resolution.

Key Requirements

•Complete bachelor’s in computer science or computer Engineering or equivalent experience.
•Experience with Software development: 2 years
•Knowledge and experience with Object-oriented programming.
•Solid advanced data structures and algorithms knowledge.
•Knowledge of C/C++ programming language.

Experience:2-2 yearsMemory verificationVerification IPVIPMemory modelsEmbedded systems

Education:Bachelor's

Skills:CC++UnixObject-oriented programmingVerilogVHDLSV/UVMPythonTcl

Languages:EnglishPortuguese

Tech Stack:CC++UnixSV/UVMVerilogVHDLPythonTclDDRLPDDRHBMGDDR

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor