ENGINEER, EUV PROCESS
Taiwan
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityEducation: bachelorsSkills: ["Problem-solving","Collaboration","Communication","Adaptability"]Develop and optimize EUV process modules for next-generation memory devices, including advanced process development, reticle and layout, OPC, process window analysis, and overlay optimization. Lead introduction of new technologies into manufacturing to improve yield and cycle time while expanding tool capabilities. Partner with R&D and HVM teams globally and provide on-site support with DRAM development site leaders to ensure seamless integration and execution.
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